An integrated circuit chip is bonded to a support. The chip includes a first connection pad and two second connection pads. The support includes a third connection pad and two fourth connection pads. A stack layers includes first, second, and third conductive layers and insulating layers. The first, second, and third conductive layers are separated from one another by the insulating layers. The second conductive layer is positioned between the first and third conductive layers. The first and third conductive layers electrically connect the two second connection pads to the two fourth connection pads. The second conductive layer electrically connects the first connection pad to the third connection pad.

A semiconductor package substrate includes an insulating substrate, a circuit pattern on the insulating substrate, a protective layer formed on the insulating substrate to cover the circuit pattern on the insulating substrate, a pad formed on the protective layer while protruding from a surface of the protective layer, and an adhesive member on the pad.

A semiconductor device comprises: a substrate having a set of conductive patterns; a semiconductor die mounted on the substrate, wherein the semiconductor die has on its top surface a set of bonding pads; and a conductive bar assembly for electrically connecting the set of conductive patterns of the substrate with the set of bonding pads of the semiconductor die, wherein the conductive bar assembly comprises: an insulating body; and a set of conductive bars extending within the insulating body, wherein the set of conductive bars have a set of first ends exposed from a first surface of the insulating body to be electrically connected to the set of conductive patterns of the substrate and a set of second ends exposed from a second surface of the insulating body to be electrically connected to the set of bonding pads of the semiconductor die.

An integrated circuit (IC) package that includes a first die, a wire bond coupled to the first die, a first encapsulation layer that at least partially encapsulates the first die and the wire bond, a second die, a redistribution portion coupled to the second die, and a second encapsulation layer that at least partially encapsulates the second die. In some implementations, the wire bond is coupled to the redistribution portion. In some implementations, the integrated circuit (IC) package further includes a package interconnect that is at least partially encapsulated by the second encapsulation layer. In some implementations, the integrated circuit (IC) package further includes a via that is at least partially encapsulated by the second encapsulation layer. In some implementations, the integrated circuit (IC) package has a height of about 500 microns (m) or less.

Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a multi-chip module (MCM) is disclosed. The MCM includes a common substrate and a first integrated circuit (IC) chip disposed on the common substrate. The first IC chip includes a first memory interface. A second IC chip is disposed on the common substrate and includes a second memory interface. A first memory device is disposed on the common substrate and includes memory and a first port coupled to the memory. The first port is configured for communicating with the first memory interface of the first IC chip. A second port is coupled to the memory and communicates with the second memory interface of the second IC chip. In-memory processing circuitry is coupled to the memory and controls transactions between the first memory device and the first and second IC chips.