A semiconductor package includes a semiconductor die including circuitry electrically coupled to bond pads that is mounted onto a leadframe. The leadframe includes a plurality of leads and a dam bar having a transverse portion that extends between adjoining ones of the leads. The bond pads are electrically connected to the plurality of leads. A raised dam pattern is on the dam bar or on an edge of an exposed portion of a top side clip of the semiconductor package that is positioned above and connects to the semiconductor die. The raised dam pattern includes a first material that is different relative to the material of the dam bar or the clip. A mold material encapsulates the semiconductor die.

A semiconductor package includes a semiconductor die including circuitry electrically coupled to bond pads that is mounted onto a leadframe. The leadframe includes a plurality of leads and a dam bar having a transverse portion that extends between adjoining ones of the leads. The bond pads are electrically connected to the plurality of leads. A raised dam pattern is on the dam bar or on an edge of an exposed portion of a top side clip of the semiconductor package that is positioned above and connects to the semiconductor die. The raised dam pattern includes a first material that is different relative to the material of the dam bar or the clip. A mold material encapsulates the semiconductor die.

A circuit includes a field effect transistor (FET), a reference transistor having an output coupled to an output of the FET, an active bias circuit coupled to the reference transistor and configured to generate an input signal for the reference transistor in response to a change in drain current of the reference transistor due to carrier trapping and to apply the input signal to an input of the reference transistor, and a summing node coupled to an input of the FET and to the input of the reference transistor. The summing node adds the input signal to an input signal of the FET to compensate the carrier trapping effect.

A circuit includes a field effect transistor (FET), a reference transistor having an output coupled to an output of the FET, an active bias circuit coupled to the reference transistor and configured to generate an input signal for the reference transistor in response to a change in drain current of the reference transistor due to carrier trapping and to apply the input signal to an input of the reference transistor, and a summing node coupled to an input of the FET and to the input of the reference transistor. The summing node adds the input signal to an input signal of the FET to compensate the carrier trapping effect.

A first package is bonded to a first substrate with first external connections and second external connections. The second external connections are formed using materials that are different than the first external connections in order to provide a thermal pathway from the first package. In a particular embodiment the first external connections are solder balls and the second external connections are copper blocks.

A first package is bonded to a first substrate with first external connections and second external connections. The second external connections are formed using materials that are different than the first external connections in order to provide a thermal pathway from the first package. In a particular embodiment the first external connections are solder balls and the second external connections are copper blocks.

In a method of manufacturing a semiconductor package, a first semiconductor device is arranged on a package substrate. An electrostatic discharge structure is formed on at least one ground substrate pad exposed from an upper surface of the package substrate. A plurality of second semiconductor devices is stacked on the package substrate and spaced apart from the first semiconductor device, the electrostatic discharge structure being interposed between the first semiconductor device and the plurality of second semiconductor devices. A molding member is formed on the package substrate to cover the first semiconductor device and the plurality of second semiconductor devices.

In a method of manufacturing a semiconductor package, a first semiconductor device is arranged on a package substrate. An electrostatic discharge structure is formed on at least one ground substrate pad exposed from an upper surface of the package substrate. A plurality of second semiconductor devices is stacked on the package substrate and spaced apart from the first semiconductor device, the electrostatic discharge structure being interposed between the first semiconductor device and the plurality of second semiconductor devices. A molding member is formed on the package substrate to cover the first semiconductor device and the plurality of second semiconductor devices.

A semiconductor chip may include: a body portion with a front surface and a rear surface; a pair of through electrodes penetrating the body portion; an insulating layer disposed over the rear surface of the body portion and the pair of through electrodes; and a rear connection electrode disposed over the insulating layer and connected simultaneously with the pair of through electrodes, wherein a distance between the pair of through electrodes is greater than twice a thickness of the insulating layer.

A semiconductor chip may include: a body portion with a front surface and a rear surface; a pair of through electrodes penetrating the body portion; an insulating layer disposed over the rear surface of the body portion and the pair of through electrodes; and a rear connection electrode disposed over the insulating layer and connected simultaneously with the pair of through electrodes, wherein a distance between the pair of through electrodes is greater than twice a thickness of the insulating layer.