Methods of forming microelectronic package structures/modules, and structures formed thereby, are described. Structures included herein may include a die on a first substrate, at least one first component adjacent the die on the first substrate, and molding material on the first substrate, wherein the at least one component and the die are embedded in the molding material. A second substrate may be physically coupled to the first substrate. A communication structure may be disposed on a top surface of the second substrate, wherein at least one second component may also be located on the top surface of the second substrate.

The present invention discloses a packaging structure for large-size chips adapted to small-size packages and a processing method thereof, wherein the first solder pad cavity and the second solder pad cavity are intersected and misaligned; the channel is located on one side of the two solder pad cavities, with the inner wall of the channel being a metallized hole wall; by providing a channel with a metallized hole wall on the proximal side of the packaging structure, more space is provided for chips, which meets the processing needs for large-size chips adapted to small-size packages.

A method of manufacturing a laminated assembly includes depositing an oxide film on each of one surface of a plate-shaped object and a temporary joint surface of a temporary support substrate in an atmosphere whose temperature is kept in a first temperature range, performing a hydrophilizing process on an exposed surface of the oxide film, temporarily joining the plate-shaped object and the temporary support substrate with the oxide film interposed therebetween, forming a joint member on a joint surface of a support substrate, joining the plate-shaped object and the support substrate to each other with the joint member interposed therebetween, vaporizing water contained in the oxide film in an atmosphere whose temperature is kept in a second temperature range higher than the first temperature range, and separating the plate-shaped object and the temporary support substrate from each other.

A semiconductor device having a first dielectric layer and a redistribution layer. The redistribution layer has sidewalls and is formed on a passivation layer of the semiconductor device. The first dielectric layer covers the sidewalls of the redistribution layer. The first dielectric layer is insulative and has a physical property of stopping the migration of the redistribution layer.

Embodiments of the present invention relate to nano-copper pillar interconnects. Nano-copper material is a mixture of nano-copper particles and one or more organic fluxes. In some embodiments, the one or more organic fluxes include organic solvents that help bind the nano-copper particles together and allow the nano-copper material to be printable. The nano-copper material is applied onto bond pads on a printed circuit board (PCB) via a printing process, a dipping process or the like, to form nano-copper covered PCB bond pads. A component can thereafter be coupled with the PCB at the nano-copper covered PCB bond pads. What is left when the solvents evaporate are nano-copper pillar interconnects that form, coupling the component with the PCB bond pads. The nano-copper pillar interconnects are of pure copper.

A power semiconductor device includes: a die carrier; a power semiconductor die arranged on the die carrier and having a first side and an opposite second side, the first side facing away from the die carrier and including a first power terminal having a Cu layer and the second side including a second power terminal electrically coupled to the die carrier; a contact clip electrically coupled to the Cu layer of the first power terminal by a solder joint; and a patterned cover layer deposited on the first side of the power semiconductor die. The cover layer surrounds the first power terminal on at least one lateral side. The cover layer is arranged over the Cu layer. The cover layer consists of Al.sub.2O.sub.3 or SiO.sub.2.

A packaging structure includes an intermediary board including opposed a first bonding surface and a second bonding surface, one or more device chips bonded on the first bonding surface of the intermediary board, and an interconnection chip bonded on the second bonding surface of the intermediary board. The intermediary board includes a plurality of interconnection unit areas, and the adjacent interconnection unit areas are spaced apart from each other. An interconnection structure is formed within the interconnection unit area. The device chips are electrically connected to the interconnection structures. The interconnection chip is disposed on the intermediary board between the adjacent interconnection unit areas and electrically connected to the interconnection structures of the adjacent interconnection unit areas.

A semiconductor device includes: a heat sink; an insulating substrate; a bonding material; and a semiconductor element, wherein the insulating substrate is bonded to an upper surface of the heat sink through the bonding material, the semiconductor element is bonded to an upper surface of the insulating substrate, a thickness of the heat sink differs depending on a position of the heat sink in the in-plane direction, supporters are disposed on the upper surface of the heat sink, in a region in which the insulating substrate is bonded to the heat sink, and each of the supporters is in contact with the insulating substrate, and the upper surface of the heat sink is not parallel to the upper surface of the insulating substrate, in a region overlapping with the region in which the insulating substrate is bonded to the heat sink in a plan view.

A non-conductive film, a semiconductor device and a manufacturing method of the same. The non-conductive film includes an adhesive layer including a thermoplastic resin, a thermosetting resin, a curing agent, and an inorganic filler, and the adhesive layer has a Y of Equation 1 that is 0 and 3:

[00001]$\begin{array}{cc}Y={\left(T*G\right)}^2/\left(5.88*\right)& \left[\mathrm{Equation}1\right]\end{array}$

where T is the difference between the heat-generation start temperature and the maximum heat-generation temperature of the adhesive layer measured by differential scanning calorimetry at a temperature increase rate of 10 C./min and a temperature of 30 C. to 300 C., G is the adhesive layer gelling time at 200 C., and is the adhesive layer minimum melt viscosity in Pa.Math.s. The non-conductive film can effectively prevent generation of voids during the semiconductor manufacturing process and sufficiently adheres to the semiconductor element, thereby providing a semiconductor device having excellent reliability.

In some aspects, an integrated circuit (IC) includes a substrate, a plurality of pads including at least two deep trench capacitor (DTC) pads disposed on the substrate, a plurality of first metal layer contacts disposed on the DTC pads, a first solder resist (SR) layer disposed on the substrate, the pads and the first metal layer contacts, a plurality of second metal layer contacts disposed on the first metal layer contacts, a second SR layer disposed on the first SR layer and the second metal layer contacts, and a DTC coupled to the second metal layer contacts.