This application provides semiconductor structures and methods of manufacturing the same. A semiconductor structure includes: an N-type semiconductor layer, a light emitting layer, and a P-type ion doped layer that are disposed from bottom to up, wherein the P-type ion doped layer comprises an activated region and non-activated regions located on two sides of the activated region, P-type doping ions in the activated region are activated, and P-type doping ions in the non-activated region are passivated. The layout of the activated region and the non-activated regions makes an LED include: a high-efficiency light emitting region and light emitting obstacle regions located on two sides of the high-efficiency light emitting region.

A method for forming a common electrode is provided, including: a) providing a support substrate on which rest optoelectronic devices separated by trenches; b) forming a dielectric layer on front faces, flanks, and a bottom of the trenches, of a thickness E1 and a thickness E2, which is less than the thickness E1, at, respectively, the front faces and the flanks; c) etching a thickness E3 of the dielectric layer, so as to uncover the flanks at a first section of the trenches; d) forming a metal layer filling the trenches and covering the front faces; and e) performing a mechanochemical polishing of the metal layer, the polishing stopping on a portion of the dielectric layer, the metal layer remaining in the trenches forming the common electrode.

A display apparatus is provided. The display apparatus includes a substrate, a transistor, a metal layer, and a light-emitting diode. The transistor is disposed on the substrate. The metal layer is disposed on the transistor and electrically connected to the transistor, wherein a first distance is between the upper surface of the metal layer and the substrate in a direction perpendicular to the substrate. The light-emitting diode is disposed on the metal layer, wherein the light-emitting diode includes a light-emitting diode body and an electrode, the light-emitting diode body is electrically connected to the metal layer via the electrode, the light-emitting diode body has a first surface and a second surface opposite to the first surface, the first surface and the second surface are parallel to the substrate, and in the direction above, a second distance is between the first surface and the second surface, wherein the ratio of the second distance to the first distance is greater than or equal to 0.25 and less than or equal to 6.

Direct-bonded LED arrays and applications are provided. An example process fabricates a LED structure that includes coplanar electrical contacts for p-type and n-type semiconductors of the LED structure on a flat bonding interface surface of the LED structure. The coplanar electrical contacts of the flat bonding interface surface are direct-bonded to electrical contacts of a driver circuit for the LED structure. In a wafer-level process, micro-LED structures are fabricated on a first wafer, including coplanar electrical contacts for p-type and n-type semiconductors of the LED structures on the flat bonding interface surfaces of the wafer. At least the coplanar electrical contacts of the flat bonding interface are direct-bonded to electrical contacts of CMOS driver circuits on a second wafer. The process provides a transparent and flexible micro-LED array display, with each micro-LED structure having an illumination area approximately the size of a pixel or a smallest controllable element of an image represented on a high-resolution video display.

Described are light emitting diode (LED) devices comprising a plurality of mesas defining pixels, each of the mesas comprising semiconductor layers, an N-contact material in a space between each of the plurality of mesas, a dielectric material which insulates sidewalls of the P-type layer and the active region from the metal. A hard mask layer is above the semiconductor layers, the hard mask layer having a plurality of openings therein, each partially filled with a liner layer and partially filled with a P-metal material plug, the P-metal material plug having a width; and a passivation film is on the hard mask layer, the passivation film having a plurality of passivation film openings therein defining a width, the width of each passivation film opening being less than the width of a combination of the P-metal material plug and the liner layer.

A method of forming a sandwich passivation layer (405) on a semiconductor device (400) comprising a bond pad (404) is provided. The method comprises forming a first layer (406) over a surface of the semiconductor device (400), removing a part of the first layer (406) to expose a surface of the bond pad (404), forming a second layer (407) over the first layer (406) and the surface of the bond pad (404), and forming a third layer (408) over the second layer (407), wherein the surface of the bond pad (404) is not in contact with the first layer (406) or third layer (408).

An embodiment of the present invention provides an element transferring method that may increase a yield of transferring an element, and an electronic panel manufacturing method using the same. The element transferring method includes: preparing a carrier film in which a first surface of an element on which a terminal is formed is adhered to an adhesive surface; providing a cover adhesive layer on the adhesive surface so that the second surface of the element that is opposite to the first surface and where the terminal is not formed is covered; transferring the element to the target substrate by adhering the cover adhesive layer to the target substrate while the second surface is facing the target substrate; and separating the carrier film from the element, wherein in transferring the element, the carrier film is pressed so that the surface of the cover adhesive layer is flat at the same height as the terminal.

One or more systems and/or methods are disclosed for building a relief print generator with no bezel. An electrode layer having more than one electrode can be used in an electrode-based, electro-luminescence component of the relief print generator. The respective electrodes may be connected to power sources with different voltage phases. An electrical circuit can be created between a biometric object and more than one electrode in the electrode layer when the biometric object contacts a surface of the generator. The electro-luminescent component can be activated by electrical charge and emit light indicative of a relief print of the biometric object. A contact electrode outside the electrode layer may not be used, which may allow for the removal of a bezel from an example device.

A light-emitting chip and a method for manufacturing the same are provided. Top surfaces of a first semiconductor layer (11), a first active layer (12), a second semiconductor layer (13) and a substrate (14) included in the light-emitting chip are located on a first horizontal plane, and bottom surfaces of the first semiconductor layer (11), the first active layer (12), the second semiconductor layer (13) and the substrate (14) included in the light-emitting chip are located on a second horizontal plane; and the top surfaces of the first semiconductor layer (11), the first active layer (12), the second semiconductor layer (13) and the substrate (14) serve as light-emitting surfaces.

An inorganic coating may be applied to bond optically scattering particles or components. Optically scattering particles bonded via the inorganic coating may form a three dimensional film which can receive a light emission, convert, and emit the light emission with one or more changed properties. The inorganic coating may be deposited using a low-pressure deposition technique such as an atomic layer deposition (ALD) technique. Two or more components, such as an LED and a ceramic phosphor layer may be bonded together by depositing an inorganic coating using the ALD technique.