An antenna element includes a balun configured to convert an unbalanced signal to a balanced signal and having an input, a first output, and a second output. The antenna element further includes a feed layer having a first feed coupled to the first output of the balun, a second feed coupled to the second output of the balun, a first ridge coupled to the first feed, a second ridge coupled to the second feed, and a center post.

An antenna element includes a balun configured to convert an unbalanced signal to a balanced signal and having an input, a first output, and a second output. The antenna element further includes a feed layer having a first feed coupled to the first output of the balun, a second feed coupled to the second output of the balun, a first ridge coupled to the first feed, a second ridge coupled to the second feed, and a center post.

Baluns with integrated matching networks are provided herein. In certain embodiments, a balun structure includes a first pair of coupled lines, a second pair of coupled lines and a transmission line. Additionally, a first port of the balun is connected to a reference voltage by way of a first line of the first pair of coupled lines, the transmission line, and a first line of the second pair of coupled lines. Furthermore, a second port of the balun is connected to the reference voltage by way of a second line of the first pair of coupled lines, while a third port of the balun is connected to the reference voltage by way of a second line of the second pair of coupled lines. The first port serves as an unbalanced signal terminal, while the second port and the third port serve as positive and negative signal terminals.

A radio frequency (RF) aperture includes an interface printed circuit board. An array of electrically conductive tapered projections have bases disposed on a front side of the interface printed circuit board and extend away from the front side of the interface printed circuit board. Chip baluns are mounted on the back side of the interface printed circuit board. Each chip balun has a balanced port electrically connected with two neighboring electrically conductive tapered projections via electrical feedthroughs passing through the interface printed circuit board. Each chip balun further has an unbalanced port, and RF circuitry disposed at the back side of the interface printed circuit board is electrically connected with the unbalanced ports of the chip baluns. The electrically conductive tapered projections include dielectric tapered projections and an electrically conductive layer disposed on an inner or outer surface of the dielectric tapered projections.

A radio frequency (RF) aperture includes an interface printed circuit board. An array of electrically conductive tapered projections have bases disposed on a front side of the interface printed circuit board and extend away from the front side of the interface printed circuit board. Chip baluns are mounted on the back side of the interface printed circuit board. Each chip balun has a balanced port electrically connected with two neighboring electrically conductive tapered projections via electrical feedthroughs passing through the interface printed circuit board. Each chip balun further has an unbalanced port, and RF circuitry disposed at the back side of the interface printed circuit board is electrically connected with the unbalanced ports of the chip baluns. The electrically conductive tapered projections include dielectric tapered projections and an electrically conductive layer disposed on an inner or outer surface of the dielectric tapered projections.

A balun includes an unbalanced terminal, balanced terminals, and lines, and converts a signal between an unbalanced line and an balanced line. A first line is connected between the unbalanced terminal and a reference potential. A second line is connected between the balanced terminal and the reference potential, and is coupled to the first line. A third line is connected between the balanced terminal and the reference potential, and is coupled to the first line. A fourth line is connected in parallel to the second line, and is coupled to the third line. The fourth line is configured such that a signal with an opposite phase to that of a signal passing through the third line passes through the fourth line.

A free-from radio frequency (RF) media includes a substrate having a first dielectric layer formed thereon and a second dielectric layer on an upper surface of the first dielectric layer. A first conductive layer is formed on an upper surface of the first dielectric layer and has a first overall profile. A second conductive layer having a second overall profile is formed on an upper surface of the second dielectric layer such that the second dielectric layer is interposed between the first and second conductive layers. The first overall profile of the first conductive layer is different from the second overall profile of the second conductive layer.

Microelectronic assemblies that include a lithographically-defined substrate integrated waveguide (SIW) component, and related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate portion having a first face and an opposing second face; and an SIW component that may include a first conductive layer on the first face of the package substrate portion, a dielectric layer on the first conductive layer, a second conductive layer on the dielectric layer, and a first conductive sidewall and an opposing second conductive sidewall in the dielectric layer, wherein the first and second conductive sidewalls are continuous structures.

Microelectronic assemblies that include a lithographically-defined substrate integrated waveguide (SIW) component, and related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate portion having a first face and an opposing second face; and an SIW component that may include a first conductive layer on the first face of the package substrate portion, a dielectric layer on the first conductive layer, a second conductive layer on the dielectric layer, and a first conductive sidewall and an opposing second conductive sidewall in the dielectric layer, wherein the first and second conductive sidewalls are continuous structures.

A semiconductor chip includes a first wireless communication circuit, a local oscillator (LO) buffer, and an auxiliary path. The first wireless communication circuit has a signal path, wherein the signal path has a mixer input port and a signal node distinct from the mixer input port. The auxiliary path is used to electrically connect the LO buffer to the signal node of the signal path. The LO buffer is reused for a loop-back test function through the auxiliary path.