An aspect relates to a signal power splitter/combiner including a first signal port; a first resistor; a first impedance transformer coupled in series with the first resistor between the first signal port and a first intermediate node; a second impedance transformer coupled between the first intermediate node and a second signal port; a third impedance transformer coupled between the first intermediate node and a third signal port; and a second resistor coupled between the second and third signal ports. The signal power splitter/combiner may further include a fourth impedance transformer coupled between the second impedance transformer and the second signal port, a fifth impedance transformer coupled between the third impedance transformer and the third signal port; and a third resistor coupled between a third intermediate nod.

A new two-probe waveguide slide screw load-pull tuner of which the probes share the same waveguide section; they are inserted diametrically at fixed depth into facing each other slots on opposite broad walls of the waveguide. The tuner does not have cumbersome adjustable vertical axes controlling the penetration of the probes and its low profile is optimized for on-wafer operations. The carriages holding the probes are moved along the waveguide using electric stepper motors or linear actuators.

A new two-probe waveguide slide screw load-pull tuner of which the probes share the same waveguide section; they are inserted diametrically at fixed depth into facing each other slots on opposite broad walls of the waveguide. The tuner does not have cumbersome adjustable vertical axes controlling the penetration of the probes and its low profile is optimized for on-wafer operations. The carriages holding the probes are moved along the waveguide using electric stepper motors or linear actuators.

A power divider/combiner includes a first transmission line that includes a first part and a second part, and a second transmission line and a third transmission line that are electromagnetically coupled with the first transmission line. The first part, the second part, the second transmission line and the third transmission line are each of a particular length. The first part, the second transmission line and the third transmission line are respectively connected to a first port, a second port and a third port for inputting/outputting signals having a target wavelength equal to four times the particular length.

An antenna array is provided that includes a plurality of radiating elements and one or more combiners. The plurality of radiating elements and the combiners are formed as a single indivisible metal element by use of additive manufacturing processes.

An antenna array is provided that includes a plurality of radiating elements and one or more combiners. The plurality of radiating elements and the combiners are formed as a single indivisible metal element by use of additive manufacturing processes.

A system is disclosed herein. The system includes a splitter board. The splitter board includes a microprocessor, a converter, and a bypass relay. The converter includes analog-to-digital circuitry and digital-to-analog circuitry. The bypass relay is configurable between a first state and a second state. In the first state, the bypass relay is configured to direct an input signal to the converter. The converter converts the input signal to a converted input signal and splits the converted input signal into a first portion and a second portion. The first portion is directed to the microprocessor. The second portion is directed to an output port of the splitter board for downstream processes. In the second state, the bypass relay is configured to cause the input signal to bypass the converter. The bypass relay directs the input signal to the output port of the splitter board for the downstream processes.

A system is disclosed herein. The system includes a splitter board. The splitter board includes a microprocessor, a converter, and a bypass relay. The converter includes analog-to-digital circuitry and digital-to-analog circuitry. The bypass relay is configurable between a first state and a second state. In the first state, the bypass relay is configured to direct an input signal to the converter. The converter converts the input signal to a converted input signal and splits the converted input signal into a first portion and a second portion. The first portion is directed to the microprocessor. The second portion is directed to an output port of the splitter board for downstream processes. In the second state, the bypass relay is configured to cause the input signal to bypass the converter. The bypass relay directs the input signal to the output port of the splitter board for the downstream processes.

A method of operating a reconfigurable quadrature coupler is disclosed. The method includes determining a first switchable impedance to provide a second port reflection coefficient by operating a coupled port transformer, which coupled port transformer is coupled to a second port having a coupled port transmission line connected to a first transistor; determining a second switchable impedance to provide a third port reflection coefficient by operating an isolation port transformer, which isolation port transformer is coupled to a third port having an isolation port transmission line connected to a second transistor; and determining a fourth switchable impedance to provide a fourth port reflection coefficient by operating a through port transformer, which through port transformer is coupled to a fourth port having a through port transmission line connected to a third transistor, and switching on or off selected ones of the first, second, and third transistors by operating a controller.

A method of operating a reconfigurable quadrature coupler is disclosed. The method includes determining a first switchable impedance to provide a second port reflection coefficient by operating a coupled port transformer, which coupled port transformer is coupled to a second port having a coupled port transmission line connected to a first transistor; determining a second switchable impedance to provide a third port reflection coefficient by operating an isolation port transformer, which isolation port transformer is coupled to a third port having an isolation port transmission line connected to a second transistor; and determining a fourth switchable impedance to provide a fourth port reflection coefficient by operating a through port transformer, which through port transformer is coupled to a fourth port having a through port transmission line connected to a third transistor, and switching on or off selected ones of the first, second, and third transistors by operating a controller.