H02H3/027

TIMER CIRCUIT WITH AUTONOMOUS FLOATING OF PINS AND RELATED SYSTEMS, METHODS, AND DEVICES
20210159688 · 2021-05-27 ·

An electrical system includes an integrated circuit device including input/output (I/O) pins, a reset circuit, and an I/O circuit. The I/O circuit is operably coupled to the I/O pins. The I/O circuit is configured to selectively operate the I/O pins in an electrically floating state responsive to a system reset signal transmitted by the reset circuit. The I/O circuit is further configured to selectively operate the I/O pins in the electrically floating state responsive to a signal provided by a timer circuit independently from the reset circuit.

TIMER CIRCUIT WITH AUTONOMOUS FLOATING OF PINS AND RELATED SYSTEMS, METHODS, AND DEVICES
20210159688 · 2021-05-27 ·

An electrical system includes an integrated circuit device including input/output (I/O) pins, a reset circuit, and an I/O circuit. The I/O circuit is operably coupled to the I/O pins. The I/O circuit is configured to selectively operate the I/O pins in an electrically floating state responsive to a system reset signal transmitted by the reset circuit. The I/O circuit is further configured to selectively operate the I/O pins in the electrically floating state responsive to a signal provided by a timer circuit independently from the reset circuit.

PRIMARY AND SYSTEM PROTECTION FOR AN ELECTRIC POWER DELIVERY SYSTEM

Primary protection relays and an integrator disclosed for providing primary protection and secondary applications for an electric power delivery system. The primary protection relays obtain signals from, and provide primary protection operations for the power system, and may operate independently from the integrator. An integrator receives signals and status communications from the primary protection relays to perform secondary applications for the electric power delivery system. The secondary applications may include backup protection, system protection, interconnected protection, and automation functions.

PRIMARY AND SYSTEM PROTECTION FOR AN ELECTRIC POWER DELIVERY SYSTEM

Primary protection relays and an integrator disclosed for providing primary protection and secondary applications for an electric power delivery system. The primary protection relays obtain signals from, and provide primary protection operations for the power system, and may operate independently from the integrator. An integrator receives signals and status communications from the primary protection relays to perform secondary applications for the electric power delivery system. The secondary applications may include backup protection, system protection, interconnected protection, and automation functions.

Low-loss and fast acting solid-state breaker

A circuit including a source, a load, and an isolation circuit for controllably isolating the load from the source. The isolation circuit is disposed between the source and the load. The isolation circuit includes at least one insulated-gate bipolar transistor (IGBT) and at least one gate turn-off thyristor (GTO) in parallel with the insulated-gate bipolar transistor. When no fault condition exists, the GTO is configured to be ON to couple the load to the source. When a fault condition exists, the at least one IGBT is configured to turn ON. After the at least one IGBT turns ON, the at least one GTO is configured to turn OFF. After a predetermined amount of time, reflecting the post fabrication alteration to the GTO's minority carrier lifetime (e.g. electron irradiation), after the at least one GTO turns OFF, the at least one IGBT is configured to turn OFF. Alternatively, the circuit is used as an inverter switch, where at the command to turn ON is supplied, the at least one IGBT is turned ON, followed by the at least one SGTO. When commanded to turn OFF the at least one SGTO is turned OFF followed by the at least one IGBT. This alternative configuration allows the robust, controllable switching speeds of IGBTs and the superior conduction efficiency of SGTOs. The two configurations mentioned above utilize a wide range of SGTO performance, thus the ability to control the SGTOs turn-off speed by reducing its minority carrier lifetime after the device is processed is of large importance. The efficiency of all uses of the circuit can be optimized with the judicious selection of SGTO minority carrier lifetime and the ratio of active area between the SGTO and IGBT devices. In all cases there is a balance between the time the circuit can achieve hard turn-off without current commutation, the conduction efficiency of the circuit and the maximum amount of controllable current. In all cases both the conduction efficiency of the circuit is higher than an IGBT-only based circuit, and the switching performance is higher than a GTO-only based circuit.

Low-loss and fast acting solid-state breaker

A circuit including a source, a load, and an isolation circuit for controllably isolating the load from the source. The isolation circuit is disposed between the source and the load. The isolation circuit includes at least one insulated-gate bipolar transistor (IGBT) and at least one gate turn-off thyristor (GTO) in parallel with the insulated-gate bipolar transistor. When no fault condition exists, the GTO is configured to be ON to couple the load to the source. When a fault condition exists, the at least one IGBT is configured to turn ON. After the at least one IGBT turns ON, the at least one GTO is configured to turn OFF. After a predetermined amount of time, reflecting the post fabrication alteration to the GTO's minority carrier lifetime (e.g. electron irradiation), after the at least one GTO turns OFF, the at least one IGBT is configured to turn OFF. Alternatively, the circuit is used as an inverter switch, where at the command to turn ON is supplied, the at least one IGBT is turned ON, followed by the at least one SGTO. When commanded to turn OFF the at least one SGTO is turned OFF followed by the at least one IGBT. This alternative configuration allows the robust, controllable switching speeds of IGBTs and the superior conduction efficiency of SGTOs. The two configurations mentioned above utilize a wide range of SGTO performance, thus the ability to control the SGTOs turn-off speed by reducing its minority carrier lifetime after the device is processed is of large importance. The efficiency of all uses of the circuit can be optimized with the judicious selection of SGTO minority carrier lifetime and the ratio of active area between the SGTO and IGBT devices. In all cases there is a balance between the time the circuit can achieve hard turn-off without current commutation, the conduction efficiency of the circuit and the maximum amount of controllable current. In all cases both the conduction efficiency of the circuit is higher than an IGBT-only based circuit, and the switching performance is higher than a GTO-only based circuit.

Energy storage and power supply system with reserve mode and override

An energy storage and power supply device includes an energy storage unit, an output coupled to the energy storage unit, and a processing circuit. The energy storage unit is configured to store electrical energy. The output is configured to facilitate providing power from the energy storage unit to a load. The processing circuit is configured to selectively restrict a power flow provided to the output by the energy storage unit in response to an operating characteristic of the energy storage and power supply device satisfying a threshold condition.

Energy storage and power supply system with reserve mode and override

An energy storage and power supply device includes an energy storage unit, an output coupled to the energy storage unit, and a processing circuit. The energy storage unit is configured to store electrical energy. The output is configured to facilitate providing power from the energy storage unit to a load. The processing circuit is configured to selectively restrict a power flow provided to the output by the energy storage unit in response to an operating characteristic of the energy storage and power supply device satisfying a threshold condition.

A NANO GRID PROTECTION DEVICE, LARGE POWER GRID AND A METHOD FOR CONTROLLING A NANO GRID PROTECTION DEVICE

Provided is a nano grid protection device for a nano grid including a distributed power supply, a large power grid including the nano grid protection device, and a method for controlling the nano grid protection device. In an embodiment, the nano grid is connected with a bus through the nano grid protection device and a main grid is connected with the bus through a main grid protection device. In an embodiment, the nano grid protection device includes: a signal unit, configured to detect and send current information passing through the nano grid protection device, the current information including the magnitude and direction of the current; a controller, configured to determine, based upon the received current information, whether to send a trip signal or not; and an execution mechanism, configured to execute a trip operation of the nano grid protection device upon receiving the trip signal.

OVER-VOLTAGE PROTECTION METHOD AND DEVICE
20210028617 · 2021-01-28 ·

Embodiments of the present disclosure provide an over-voltage protection method, an over-voltage protection device and a display device. When the voltage value of the output signal is greater than the first preset voltage threshold, it is determined whether the voltage value of the output signal meets the preset over-voltage protection condition. If the voltage value of the output signal is detected to meet the preset over-voltage protection condition, the first control signal is output to stop output of the output signal or lower the voltage value of the output signal.