An electronic device includes a monitoring unit that monitors a voltage of a first terminal that receives power supplied from a power supply apparatus, and a control unit that performs control so as to stop the power supply from the power supply apparatus if a voltage variation per unit time of the first terminal is not less than a first predetermined value or the voltage of the first terminal is not less than a second predetermined value.

A motor control apparatus for controlling a power supply to an electrical motor (M) connected to an output terminal (3) of the motor control apparatus (1) comprising: an overcurrent protection circuit (1A) having a power switch (5) through which the electrical motor (M) receives an electrical load current (I.sub.L) and having a sensor component (4) connected in series with the power switch (5) and adapted to generate directly a voltage drop (?U.sub.4) corresponding to the current rise speed of the electrical load current (I.sub.L) flowing from an input terminal (2) of the motor control apparatus (1) via the sensor component (4) and the power switch (5) to the output terminal (3) and having a driver circuit (6) adapted to detect an occurring overcurrent depending on the voltage drop (?U.sub.4) generated by the sensor component (4) and/or depending on a voltage drop (?U.sub.5) along the power switch (5) and adapted to switch off said power switch (5) upon detection of an overcurrent within a switch-off period of less than one millisecond; and/or comprising a power supply control circuit (10) having a sensor component (9) adapted to measure at the input terminal (2) a supply voltage notified to a control unit (8) of the motor control apparatus (1) adapted to control an electrical power supplied to the electrical motor (M) depending on an operation mode of the electrical motor (M).

A load protection apparatus for protecting an electrical load connected to an output terminal of the load protection apparatus against overcurrent, includes an overcurrent protection circuit having a power switch through which the electrical load receives an electrical load current via the output terminal and having a sensor component connected in series with the power switch. The sensor component is adapted to directly generate a voltage drop corresponding to the current rise speed of the electrical load current flowing from an input terminal of the load control apparatus, via the sensor component and the power switch to the output terminal. The sensor component further includes a driver circuit adapted to detect an occurring overcurrent depending on the voltage drop generated by the sensor component and depending on a voltage drop along the power switch adapted to switch off said power switch upon detection of an overcurrent within a switch-off period.

A solid-state circuit interrupter and arc prevention device (SSI/APD) is disclosed. The SSI/APD is designed to be configured in series with a mechanical circuit breaker and serves to interrupt current flowing through the circuit it is protecting upon a short circuit being detected or if an overload has persisted for an inordinate amount of time. The SSI/APD is capable of detecting and responding to faults in a matter of microseconds and detects and responds to faults on its own, without requiring the mechanical circuit breaker to trip. The mechanical circuit breaker can be optionally tripped after the SSI/APD has opened the circuit. However, the mechanical circuit breaker is tripped only after the SSI/APD has interrupted the circuit, so electrical arcing across the circuit breaker's contacts is avoided. The SSI/APD can also be reset remotely after a fault has been cleared, obviating the need for a person to be present to reset it.

A method for circuit breaker failure (CBF) protection in a power substation is disclosed. The power substation includes a first circuit breaker (CB), a second CB coupled to the first CB, a feeder coupled to the first CB and the second CB, a power plant coupled to the feeder, a first plurality of CBs coupled to the first CB, and a second plurality of CBs coupled to the second CB. The method includes sending a first stage tripping command to the first CB and the second CB to trip the first CB and the second CB responsive to a non-high current tripping command being active for a first period of time, and one of a current condition and an energization condition being satisfied for the first period of time, sending a first second-stage tripping command to the first plurality of CBs to trip the first plurality of CBs responsive to the non-high current tripping command being active for a second period of time, and one of the current condition and the energization condition being satisfied for the second period of time, and sending a second second-stage tripping command to the second plurality of CBs to trip the second plurality of CBs responsive to the non-high current tripping command being active for a third period of time, and one of the current condition and the energization condition being satisfied for the third period of time. The second period of time and the third period of time may be longer than the first period of time.

A passive electronic fuse for protecting a DC application in the event of a fault includes a first leg including a first winding of a mutual inductor and a switch device connected in series, a second leg including a second winding of the mutual inductor. The first leg and the second leg are connected in parallel and a self-inductance of the second winding is lower than a self-inductance of the first winding. The second leg further includes a capacitor connected in series with the second winding of the mutual inductor, and the switch device is a thyristor or a switch device with switching properties of a thyristor.

A phase shifter includes a signal input, a signal output, an ESD protection circuit, first and second signal paths between the signal input and the signal output. The ESD protection circuit includes first and second two port devices, each two port device being switchable between a high impedance state and a low impedance state. The first signal path includes the first two port device of the ESD protection circuit and a first delay line configured to provide a first phase shift to a signal transmitted from the signal input to the signal output via the first signal path. The second signal path includes the second two port device of the ESD protection circuit and a second delay line configured to provide a second phase shift, different from the first phase shift, to the signal transmitted from the signal input to the signal output via the second signal path.

A test and measurement system includes one or more high voltage sources having a voltage high enough to be dangerous to users, an instrument backplane, having one or more backplane double fault protected interlocks, a power signal, and one or more slots configured to accept one or more modules, and one or more processors configured to execute code that causes the one or more processors to: monitor one or more signals from the one or more backplane double fault protected interlocks; and without engaging any of the one or more high voltage sources, determine an operational state and faulted condition of each of the one or more backplane double fault protected interlocks, and check wiring of an interlock pathway between the test and measurement instrument and a user system.

A passive electronic fuse for protecting a DC application in the event of a fault includes a first leg including a first winding of a mutual inductor and a switch device connected in series, a second leg including a second winding of the mutual inductor. The first leg and the second leg are connected in parallel and a self-inductance of the second winding is lower than a self-inductance of the first winding. The second leg further includes a capacitor connected in series with the second winding of the mutual inductor, and the switch device is a thyristor or a switch device with switching properties of a thyristor.

Solid-state circuit breakers and method of operating same are provided. A solid-state circuit breaker (SSCB) is configured to generate a first output representative of a current through a current path of the SSCB. An analog fault detection circuit is coupled with first output and is configured to assert a second output in response to the current exceeding a trip current level. At least one analog-to-digital converter (ADC) is configured to generate samples of the first output, where the at least one ADC has a di/dt detection bandwidth that is less than a di/dt detection bandwidth of the analog fault detection circuit. The SSCB is further configured to disable the current path through the SSCB in response to determining, asynchronously, that either the second output is being asserted by the analog fault detection circuit or the samples indicate that the current through the current path exceeds the trip current level.