Disclosed are a surge protection device and a chip constituted thereby, and a communication terminal. The surge protection device comprises an input pad and an output pad. The input pad is connected to a power supply voltage, and the output pad is connected to a ground wire. NMOS transistor groups are provided between the input pad and the output pad. The NMOS transistor groups are connected to the input pad and the output pad respectively by means of metal wires. The structures of the metal wires between the NMOS transistor groups and the input pad and the output pad respectively and/or the structures of the NMOS transistor groups are changed to reduce or cancel non-uniform turn-on of the NMOS transistor groups caused by metal wires having different lengths from the NMOS transistor groups to the input pad and the output pad respectively along a power supply voltage wire direction.

A surge protective device (SPD) assembly module includes a polymeric outer enclosure, an SPD module, a first terminal, and a second terminal. The polymeric outer enclosure defines an enclosed, environmentally sealed enclosure chamber. The SPD module is disposed in the enclosure chamber. The SPD module defines an environmentally sealed SPD chamber and includes: first and second electrically conductive electrode members; and a varistor member formed of a varistor material and electrically connected between the first and second electrode members. The varistor member is disposed in the SPD chamber between the first and second electrode members. The first terminal is electrically connected to the first electrode member and extending out from the outer enclosure. The second terminal is electrically connected to the second electrode member and extending out from the outer enclosure.

The present invention discloses parallel, series and hybrid ESD protection circuits. A preferred parallel ESD protection circuit comprises a plurality of ESD devices connected in parallel, with each comprising a resistor and an OTS component connected in series. A preferred series ESD protection circuit comprises a plurality of ESD devices connected in series, wherein the OTS components in all ESD devices are disposed on a same level. A preferred hybrid ESD protections circuit comprises ESD devices connected in parallel, as well as in series.

A surge suppression circuit for a track circuit is provided. The surge suppression circuit comprises a first surge protection device including a first pair of silicon avalanche diodes and a second surge protection device including a second pair of silicon avalanche diodes. The first surge protection device is connected on a first connection line between a first terminal of a railroad signaling electronic equipment to be protected from a surge and a first terminal of a first rail of two physical rails. The second surge protection device is connected on a second connection line between a second terminal of the railroad signaling electronic equipment and a second terminal of a second rail of the two physical rails. The first surge protection device and the second surge protection device are connected to an earth ground terminal.

In an embodiment, a power delivery system includes a first current limiter and a second current limiter in parallel with each other, wherein a direct current (DC) voltage is provided to each of the first current limiter and the second current limiter; a first transformer electrically coupled to the first current limiter; a second transformer electrically coupled to the second current limiter; first differential signal traces electrically coupled to the first transformer; and second differential signal traces electrically coupled to the second transformer, wherein the DC voltage is transmitted from the first transformer to the first differential signal traces simultaneous with the DC voltage being transmitted to the second differential signal traces by the second transformer.

The invention relates to a circuit assembly for protecting a unit to be operated from a supply network against overvoltage, comprising an input having a first and a second input connection, which are connected to the supply network, an output having a first and a second output connection, to which the unit to be protected can be connected, and a protection circuit, which is provided between the first and the second input connections in order to limit the voltage present at the first and the second input connections. According to the invention, the protection circuit has a power semiconductor, in particular an IGBT, wherein a series circuit consisting of a diac, i.e., a bidirectional electrode, and a Zener element is connected between the collector and the gate of the power semiconductor, wherein the sum of the Zener voltage and the diac voltage results in a clamping voltage for the power semiconductor, which lies above the voltage of the supply network and defines the protection level.

An ESD protection device includes a first terminal and a second terminal defining a first balanced port, a third terminal and a fourth terminal defining a second balanced port, and a ground terminal. A first coil and a third coil are provided between the first terminal and the third terminal to cancel an inductance component of a first ESD protection circuit. A second coil and a fourth coil are provided between the second terminal and the fourth terminal to cancel an inductance component of a second ESD protection circuit.

The invention relates to an overvoltage protection arrangement for information and telecommunication technology, consisting of a housing with means formed on the housing base for mounting top-hat rails, overvoltage protection elements which can be found in the housing, electric connection means, and at least one circuit board as a wiring support for the overvoltage protection elements. When viewed laterally, the housing is designed approximately in the shape of a T standing on its head and has a beam-shaped main part with a protruding head part, wherein the electric connection means can be accessed and actuated via the upper face of the beam-shaped main part. A first and second circuit board are located on a respective inner face of the lateral walls of the housing in a mutually spaced manner, and the electric connection means in the form of electric connection terminals, connection sockets, and/or plugs for example are arranged in the spacing between the first and second circuit board such that first connection means can be accessed on the horizontal plane of the beam-shaped main part and second connection means can be accessed on the vertical plane of the beam-shaped main part. The flat shape of the circuit board corresponds to the T shape of the housing or approximates the shape of the housing.

Apparatus and methods for actively-controlled trigger and latch release thyristor are provided. In certain configurations, an actively-controlled protection circuit includes an overvoltage sense circuit, a thyristor or silicon controlled rectifier (SCR) that is electrically connected between a signal node and a discharge node, and an active trigger and latch release circuit. The overvoltage sense circuit controls a voltage of a dummy supply node based on a voltage of the signal node, and the active trigger and latch release circuit detects presence of a transient overstress event at the signal node based on the voltage of the dummy supply node. The active trigger and latch release circuit provides one or more trigger signals to the SCR to control the SCR's activation voltage, and the active trigger and latch release circuit activates or deactivates the one or more trigger signals based on whether or not the transient overstress event is detected.

A composite circuit protection device includes: a first positive temperature coefficient (PTC) component; a first voltage-dependent resistor (VDR); a second VDR; and a plurality of conductive leads that correspondingly connect to the first PTC component, the first VDR and the second VDR. The second VDR and the first PTC component are electrically connected in series, the first VDR is electrically connected to the series connection of the first PTC component and the second VDR in parallel, and the first VDR has a varistor voltage greater than that of the second VDR as determined at 1 mA.