A protected capacitor system/method implementing enhanced transient over-voltage suppression is disclosed. The system/method incorporates one or more surge suppression devices (SSDs) proximally located and in parallel with a capacitor structure to produce an overall protected capacitor structure having enhanced reliability and simultaneous ability to resist transient overvoltage conditions. The SSDs are formed from series combinations of transient voltage surge suppressors (TVSs) (metal oxide varistor (MOV), diode for alternating current (DIAC), and/or silicon diode for alternating current (SIDAC)) and corresponding shunt diode rectifiers (SDRs) and placed in parallel across a capacitor structure to locally suppress voltage transients across the capacitor structure in excess of the voltage rating of the capacitor structure. The parallel shunting TVB/SDR pairs may be integrated into a printed circuit board (PCB) assembly that is externally attached to the capacitor structure or encapsulated in an enclosure incorporating the capacitor structure.

A protected capacitor system/method implementing enhanced transient over-voltage suppression is disclosed. The system/method incorporates one or more surge suppression devices (SSDs) proximally located and in parallel with a capacitor structure to produce an overall protected capacitor structure having enhanced reliability and simultaneous ability to resist transient overvoltage conditions. The SSDs are formed from series combinations of transient voltage surge suppressors (TVSs) (metal oxide varistor (MOV), diode for alternating current (DIAC), and/or silicon diode for alternating current (SIDAC)) and corresponding shunt diode rectifiers (SDRs) and placed in parallel across a capacitor structure to locally suppress voltage transients across the capacitor structure in excess of the voltage rating of the capacitor structure. The parallel shunting TVS/SDR pairs may be integrated into a printed circuit board (PCB) assembly that is externally attached to the capacitor structure or encapsulated in an enclosure incorporating the capacitor structure.

Disclosed is a complex protection device including a substrate, fuse terminals provided on the substrate, first resistive terminals provided on the substrate so as to be separated from the fuse terminals, second resistive terminals provided on the substrate opposite to the first resistive terminals across the fuse terminals, a fusible element connected to the fuse terminals, a first surface-mounted resistive element connected to the first resistive terminals, a second surface-mounted resistive element connected to the second resistive terminals, at least one printed resistive element connected to at least one of the first resistive terminals and the second resistive terminals and connected to at least one of the first surface-mounted resistive element and the second surface-mounted resistive element, and a switching element controlling flow of current to the first and second surface-mounted resistive elements and the at least one printed resistive element if overvoltage is applied.

overvoltage protector uses a low-power shunt regulator to provide precise overvoltage protection at low voltages. The shunt regulator communicates with the current limiter to the input voltage allowing precise current measurement while protecting the shunt regulator from excessive power consumption.

A varistor (50) comprising: a feed-through conductor (52) and a varistor disc (72) interposed between, and electrically connected to, conductor layers disposed on opposite surfaces of the varistor disc (72), the conductor layers being electrically isolated from one another; wherein the varistor disc (72) comprises a through aperture (60) through which the feed-through conductor extends; a first one of the conductor layers is electrically connected to the feed-through conductor; a second one of the conductor layers is, in normal use, permanently electrically connected to ground the varistor (50). This configuration enables one side of the disc (72) to be connected to the feed-through terminal, and the other side of the disc (72) to be connected to a ground plane, such as an earthed bulkhead of a wall or cabinet, via a metal plate forming part of the varistor (50) housing.

A capacitive power supply circuit including, between first and second terminals of application of an AC input voltage, a distributed capacitive structure including a plurality of elementary capacitive units, each including a current limiter series-connected with a capacitor between first and second terminals of the unit and a voltage limiter connected in parallel with the capacitor, the elementary capacitive units being series-coupled by their first and second terminals.

A transient voltage suppressor (TVS) can include an input line, a return line, and a plurality of TVS diodes disposed in series between the input line and the return line. The TVS can include a switch assembly operatively connected to the plurality of TVS diodes and configured to bypass at least one of the plurality of TVS diodes to allow a remainder of the plurality of TVS diodes to be tested at a voltage that is lower than if the switch assembly were not employed.

The disclosed technology generally relates to electrical overstress protection devices, and more particularly to electrical overstress monitoring devices for detecting electrical overstress events in semiconductor devices. In one aspect, an electrical overstress monitor and/or protection device includes a two different conductive structures configured to electrically arc in response to an EOS event and a sensing circuit configured to detect a change in a physical property of the two conductive structures caused by the EOS event. The two conductive structures have facing surfaces that have different shapes;

Methods and systems capable of launching signal-carrying transverse electromagnetic waves onto a transmission line in the higher voltage region of the transmission distribution network. Such methods and systems may include a surface wave launcher located in the higher voltage region, a network unit located in a lower voltage region, and an arrester separating the surface wave launcher and the network unit, the arrester preventing voltage from arcing over from the higher voltage region to the lower voltage region where the arrester provides the signal to the surface wave launcher.

A semiconductor device including a digital circuit, a first ground potential line provided corresponding to the digital circuit, an analog circuit, a second ground potential line respectively provided corresponding to the analog circuit, and a bidirectional diode group provided between the first ground potential line and the second ground potential line.