A method and system for suppressing EMP-induced voltage surges due to detonation of a nuclear weapon at high altitude generating an EMP (HEMP) comprising E1, E2, and E3 component pulses. Surge protection assemblies are positioned intermediate a signal stream and a plurality of electronic device ports associated with a plurality of communication channels of networked devices. Single-channel multimode surge suppressing systems are combined to form multi-port multimode protection systems that connect directly to multiport networked devices supporting communication channels with mixed signals data and direct current power in Gigabit Ethernet networks supporting PoE. The surge suppressing systems mitigate differential and common mode induced interference and protect from overvoltage surges associated with E1, E2, and E3 components of the HEMP and mitigate the over-voltages to predetermined allowable levels within the predetermined time. The surge suppressing systems is interoperable with multimode PoE and support endpoint and midspan PoE devices of Gigabit networks.

The invention relates to an overvoltage protection arrangement for information and telecommunication technology, consisting of a housing with means formed on the housing base for mounting top-hat rails, overvoltage protection elements which can be found in the housing, electric connection means, and at least one circuit board as a wiring support for the overvoltage protection elements. When viewed laterally, the housing is designed approximately in the shape of a T standing on its head and has a beam-shaped main part with a protruding head part, wherein the electric connection means can be accessed and actuated via the upper face of the beam-shaped main part. A first and second circuit board are located on a respective inner face of the lateral walls of the housing in a mutually spaced manner, and the electric connection means in the form of electric connection terminals, connection sockets, and/or plugs for example are arranged in the spacing between the first and second circuit board such that first connection means can be accessed on the horizontal plane of the beam-shaped main part and second connection means can be accessed on the vertical plane of the beam-shaped main part. The flat shape of the circuit board corresponds to the T shape of the housing or approximates the shape of the housing.

The present disclosure provides an internet interface circuit, which includes an ethernet interface, a first isolating transformer, a second isolating transformer, a network signal processing chip and a first interference defending circuit; the ethernet interface is used for receiving and sending a network signal; the first isolating transformer is used for separating a receiving data end of the ethernet interface from the network signal receiving chip; the second isolating transformer is used for separating a sending data end of the ethernet interface from the network signal receiving chip; the first interference defending circuit is used for defending common-mode interference and differential-mode interference of the receiving data end of the ethernet interface; the network signal processing chip is used for processing the network signal. The present disclosure also provides a television. The internet interface protecting circuit of the present disclosure can defend the common-mode interference and differential-mode interference.

A transient voltage protection circuit includes a first input/output pad, a second input/output pad, and a trigger circuit coupled between the first input/output pad and the second input/output pad. The trigger circuit includes a first trigger element which includes a first input/output node, a second input/output node, a third input/output node, and a first substrate diode coupled to the third input/output node of the first trigger element. The trigger circuit further includes a first resistor coupled between the first input/output node of the first trigger element and the second input/output node of the first trigger element. The trigger circuit further includes a second trigger element which includes a first input/output node, a second input/output node, a third input/output node, wherein the second input/output node of the first trigger element is coupled to the first input/output node of the second trigger element, and a second substrate diode coupled to the third input/output node of the second trigger element. The trigger circuit further includes a second resistor coupled between the first input/output node of the second trigger element and the second input/output node of the second trigger element.

A wireless power transmission device is provided. The wireless power transmission device includes a resonance signal generator and a controller. The resonance signal generator is configured to transmit wireless power to a wireless power reception device. The controller is configured to adjust the wireless power transmitted to the wireless power reception device, when a predetermined condition caused by over-voltage protection operation at the wireless power reception device is detected.

A method for preventing an electrical grid from failure in case of a temporary overvoltage includes providing an electrical grid line, a surge arrester and a disconnector device with a disconnector unit. The method further includes connecting the surge arrester at one terminal to the electrical grid line, connecting the surge arrester at its other terminal to a first terminal of the disconnector device, and connecting a second terminal of the disconnector device to ground potential. The method further includes interrupting the electrical connection in between the electrical grid line and the ground potential in response to a temporary overvoltage. The method further includes protecting the surge arrester from failure due to a thermal overload caused by the temporary overvoltage by operating the disconnector device before the surge arrester fails due to a thermal overload of the surge arrester.

A device for discharging a capacitor includes a resistive component having a resistance value selectable from among at least three resistance values. The device is configured to be connected in parallel with the capacitor. A circuit operates to select the resistance value of the resistive component.

The present disclosure relates to an electrostatic discharge (ESD) protection circuit including a dynamic field plate bias circuit, and associated methods. In some embodiments, the ESD protection circuit includes a bipolar junction transistor (BJT) based ESD protection circuit including a field plate configured to increase a breakdown voltage of the BJT based ESD protection circuit. The ESD protection circuit also includes a dynamic field plate bias circuit coupled to the field plate of the BJT based ESD protection circuit. The dynamic field plate bias circuit is configured to provide the field plate a field plate bias at transient opposite to a field plate bias at a normal operation. The transient bias reduces a trigger voltage of the BJT based ESD protection circuit and increases a shunt current of the BJT based ESD protection circuit during the ESD event. Thereby, ESD protection reliability is improved.

Provided are embodiments for a system for performing input power detection. The system includes a first input for a first power source, a second input for a second power source, and a controller that is operably coupled to the first power source and the second power source. The system also includes a first path connecting a first circuit to the first power supply, wherein the first path comprises a first field effect transistor (FET) that is operated to inhibit leakage current flow to the first circuit, and a second path connecting a second circuit to the second power supply, wherein the second path comprises a second FET that is operated to inhibit leakage current flow to the second circuit. Also provided are embodiments for a method for performing input power detection.

An electrostatic discharge (ESD) protection device includes: a first resistor coupled between a first input terminal of the ESD protection device and a first node of the ESD protection device; a second resistor coupled between the first node and a first output terminal of the ESD protection device; and a first ESD protection component coupled between the first node and a reference voltage terminal of the ESD protection device, where the reference voltage terminal is configured to be coupled to a reference voltage.