The disclosure relates to an electronic unit with a circuit board having at least one component arranged on a main surface of the circuit board and a casing element, which incorporates the at least one component, as well as with an ESD protection arrangement for the circuit board. According to the disclosure, open areas on the circuit board, which are not covered by the casing element, are covered with a gold layer directly mounted on a copper surface of the circuit board.

An electrostatic discharge protection device includes a base, a plurality of electrodes arranged on the base separated from each other, a function layer supplied on a separation space between the electrodes and a composite insulating layer disposed on the base and composed of inorganic particles dispersed in a resin, the composite insulating layer covering the electrodes and the function layer.

Methods of powering a radio that is mounted on a tower of a cellular base station are provided in which a direct current (“DC”) power signal is provided to the radio over a power cable and a voltage level of the output of the power supply is adjusted so as to provide a substantially constant voltage at a first end of the power cable that is remote from the power supply. Related cellular base stations and programmable power supplies are also provided.

A data interface with overvoltage protection circuitry includes a bus interface and power rectification stage configured to provide supply and return voltages for the data interface and overvoltage protection circuitry, a first power level overvoltage protection circuit, a second power level overvoltage protection circuit, a DALI endpoint power output port, a power supply for a DALI endpoint device drawing current from the power output port, a receiver configured to receive signals on the DALI bus, and, a transmitter configured to send signals on the DALI bus.

A driving circuit applied in a display system includes a node, a current control circuit, a protecting circuit and a timing controller, wherein the node is arranged to connect to a lighting element; the current control circuit is coupled to the node and arranged to selectively provide a current to the lighting element according to a Pulse Width Modulation (PWM) signal; the protecting circuit is coupled to the node and arranged to be selectively enabled to limit the voltage of the node according to a control signal to make the voltage of the node maintain a predetermined voltage, wherein the lighting element does not have any current passed through when the voltage of the node maintains the predetermined voltage; and the timing controller is arranged to generate the PWM signal and the control signal.

An ESD protection circuit for an input/output buffer in which when an ESD pulse or event occurs, an ESD surge on a pad is discharged to a diode and a transistor channel, thereby enhancing the efficiency of the ESD protection circuit. The ESD protection circuit includes a floating N-well bias circuit connected to a pad at an output of driver circuit and outputting a bias voltage based on or in response to a supply voltage; a switch circuit connected to a logic circuit and the driver circuit, and configured to connect and disconnect the logic circuit and the driver circuit based on or in response to the supply voltage; and a pull-down circuit connected to the driver circuit, configured to output a voltage to the driver circuit based on or in response to the supply voltage.

The present invention is concerned with pre-magnetizing a Modular Multilevel power Converters connected transformer in order to moderate inrush currents upon connecting the transformer to an electric grid. The invention takes advantage of the high amount of stored energy in MMC converters as compared to other converter types. This stored energy is used to pre-magnetize the converter-connected transformer, therefore no additional or dedicated pre-magnetizing hardware is required in addition to the charging hardware provided to charge the converter capacitors. As the transformer pre-magnetizing takes place subsequent to the converter charging, the converter charging circuit is not used to, and therefore does not need to be designed to, directly magnetize the transformer.

The present disclosure relates to a circuit providing protection against ground faults and over-voltages. The teachings thereof may be embodied in circuits including a first USB VBUS terminal; a first USB data terminal; a second USB VBUS terminal; a second USB data terminal; a VBUS line coupling the USB VBUS terminals; a data line coupling the USB data terminals; an interrupter arranged in the VBUS line or in the data line; a control circuit controlling the interrupter, comprising a breakdown member defining a first threshold voltage and a first comparison member to compare a voltage at the first USB VBUS terminal to a second threshold voltage, wherein the breakdown member connects to the first USB VBUS terminal and the switch generates an interrupt signal if: a voltage at the first USB VBUS terminal causes a voltage drop over the breakdown member exceeding the first threshold voltage, or a voltage at the first USB VBUS terminal causes a voltage applied to the first comparison member less than the second voltage threshold.

An intrinsically safe redundant regulator circuit includes a plurality of voltage limiting regulators between a regulated rail and a ground rail. Each of the plurality of voltage limiting regulators includes: (i) a shunt regulator component configured to clamp a voltage across the regulated rail and the ground rail to a safety clamp voltage value; and (ii) one or more components, where a property of each of the one or more components is selected to configure the safety clamp voltage value.

A device includes a transistor cascode circuit including a first transistor configured to pull up voltage of a bulk and a node in response to a first control signal, and a second transistor configured to pull up voltage of an interface (I/O) pin in response to a second control signal. The device further includes a third transistor configured to pull down voltage of the I/O pin in response to a third control signal, and a feedback circuit configured to turn off the first transistor when the voltage of the I/O pin is above a predetermined level during a failsafe period.