Dual mode T-switches driven by at least one low-impedance switch driver, to connect at least four wires of a multiwire bus to a multi-input comparator (MIC) of a plurality of MICs in a first mode of Orthogonal Vector Signaling operation, and in a full-duplex mode of operation, using the low-impedance switch driver to disable a corresponding subset of T-switches to selectively disconnect a pair of wires of the multiwire bus from the MIC while using low-impedance enable signal paths in the low-impedance switch drivers to shunt capacitively-coupled interfering outbound signals received at the MIC from the selectively disconnected pair of wires in the full-duplex mode of operation.

A filter network is insertable into a power transmission line, to handle disturbances in the power transmission line. A first circuit has an RC network in parallel with a surge arrestor, to bypass high frequency disturbances of the power transmission line. A second circuit has inductors for carrying low-frequency power to and from impedance injection units.

A drive device adapted to drive a semiconductor power device, wherein the drive device comprises a drive circuit comprising a first terminal adapted for connection to a first terminal of the power device, a gate terminal adapted to provide a driving signal for a gate terminal of the power device, a sensor for detecting overvoltage conditions at the first terminal of the power device, and wherein the drive circuit is adapted to modify the driving signal when the sensor detects an indication of an overvoltage condition, and wherein the drive circuit including the sensor is integrated onto a single substrate.

A system and method for detecting and isolating a high-altitude electromagnetic pulse (“HEMP”) along electrical lines electrically connected to a monitored infrastructure so as to protect the monitored infrastructure, the method including a phase unit receiving sensor signals from a plurality of sensors electrically connected to each of the electrical lines, respectively, upstream of and associated with the monitored infrastructure. The method includes determining if the received sensors signals associated with the respective electrical line is indicative of an E1 component of an EMP and, if so, actuating an isolation subsystem in less than 300 nanoseconds to electrically isolate the respective electrical line against propagation against the monitored infrastructure. Determining in real time if received sensor signals is indicative of the E1 component includes a hardware implemented neural network (NN) having algorithms for machine learning (ML) and artificial intelligence (AI) operable to provide instantaneous detection and classification.

An electrostatic discharge protection circuit includes: a pulse detection unit, a delay unit, a control unit, and a discharge unit. The pulse detection unit is configured to detect an electrostatic pulse signal; the delay unit is configured to delay or enhance driving capability of the pulse detection signal output by the pulse detection unit; the control unit is configured to generate a control signal based on a first delay signal and a second delay signal output by the delay unit; and the discharge unit is configured to open or close an electrostatic charge discharge passage based on the control signal output by the control unit.

Systems, methods, and computer program product embodiments are disclosed for performing electrophysiology (EP) signal processing. An embodiment includes an electrocardiogram (ECG) circuit board configured to process an ECG signal. The embodiment further includes a plurality of intracardiac (IC) circuit boards, each configured to process a corresponding IC signal. The ECG circuit board and the plurality of IC circuit boards share substantially a same circuit configuration and components. The ECG circuit board further processes the ECG signal using substantially a same path as each IC circuit board uses to process its corresponding IC signal.

Provided is a display substrate. The display substrate includes: a base substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of data transmission lines, a plurality of electrostatic discharge circuits, a panel crack detection trace, and a plurality of electrostatic discharge dummy circuits. At least one of the electrostatic discharge dummy circuits may be connected to the panel crack detection trace. A display device is also provided.

Electrostatic discharge protection circuitry includes a transistor pass-gate coupled between potential source of electrostatic discharge-driven current (“ESD current”) and an input node of a circuit block is configured provide a sufficiently resistive current path between a first current terminal and a second current terminal of the pass gate such that, when an amount of charge sufficient to cause an ESD event accumulates at the potential ESD current source, a sufficient voltage drop occurs across the pass gate such that devices coupled to the input node of the circuit block are protected from experiencing a voltage drop across them that is above a predetermined threshold voltage.

An electrostatic discharge (ESD) protection circuit including a monitoring unit, a main discharge transistor, and an auxiliary discharge transistor is provided herein. The monitoring unit is configured to detect an electrostatic pulse caused by accumulation of electrostatic charges. The main discharge transistor and the auxiliary discharge transistor are configured discharge the electrostatic charges to ground end after the electrostatic pulse is detected. A first section of a power supply metal line is coupled to the main discharge transistor and the auxiliary discharge transistor, a third section of the power supply metal line is coupled to an internal circuit protected by the ESD protection circuit, and a second section of the power supply metal line couples the first section to the third section. The power supply metal line includes an angle that is less than 180 degrees at a contact position between the second section and the first section.

An electrostatic discharge (ESD) protection device includes: a first resistor coupled between a first input terminal of the ESD protection device and a first node of the ESD protection device; a second resistor coupled between the first node and a first output terminal of the ESD protection device; and a first ESD protection component coupled between the first node and a reference voltage terminal of the ESD protection device, where the reference voltage terminal is configured to be coupled to a reference voltage.