A switching circuit includes a high-side transistor and a low-side transistor, each of which is of an N-channel type. A switch and a rectifying element of a PMOS transistor are provided in series between a constant voltage line through which a constant voltage is supplied and a bootstrap line. A comparison circuit operates using a high-side power supply voltage, which is a potential difference between the bootstrap line and a switching line, as a power supply to generate a detection signal indicating a magnitude relationship between the high-side power supply voltage and a threshold voltage. A level shift circuit level-shifts the detection signal down to a signal of which a ground voltage is low. A PMOS driver drives the switch asynchronously with switching of the low-side transistor in response to an output of the level shift circuit.

A power conversion apparatus includes: a first power terminal; a switching circuit including a first switching device on a path coupling a first power node to a first node, a second switching device on a path coupling the first node to a second power node, a third switching device on a path coupling the first power node to a second node, and a fourth switching device on a path coupling the second node to the second power node; a transformer including a first winding coupled to the switching circuit and a second winding; a rectifier circuit; a second power terminal; and a controller that controls operations of the switching circuit and the rectifier circuit to supply power from the second power terminal toward the first power terminal during a predetermined period different from a period during which power is supplied from the first power terminal toward the second power terminal.

A startup circuit adapted to be coupled to an input voltage supply and operable to supply an output voltage at an output terminal, the startup circuit including: a first transistor having a first control terminal, a first current terminal and a second current terminal, the first current terminal adapted to be coupled to the input voltage supply and the second current terminal coupled to the output terminal; a precharge circuit having a first terminal, a second terminal and a third terminal, the second terminal adapted to be coupled to the input voltage supply and the third terminal coupled to the first control terminal; a current limiter coupled to the precharge circuit, the first control terminal and the second current terminal; a second transistor having a second control terminal, a third current terminal and a fourth current terminal, the third current terminal coupled to the precharge circuit and the second control terminal adapted to be coupled to a control signal; and a third transistor having a third control terminal, a fifth current terminal and a sixth current terminal, the fifth current terminal coupled to the first control terminal and the third control terminal is adapted to be coupled to the control signal.

A semiconductor device includes: a semiconductor substrate of a first conductivity type; a first impurity layer of a second conductivity type formed at a surface of the semiconductor substrate; a second impurity layer of a first conductivity type formed to surround the first impurity layer of the semiconductor substrate; an insulating film configured to cover at least the first impurity layer; a resistive element provided on the insulating film and having a spiral shape; a first interlayer insulating layer configured to cover the resistive element; and a plurality of first conductive films provided on the first interlayer insulating layer and electrically coupled with the resistive element.

A pulse receiving circuit constituting a signal transmission device includes a first pulse detector that receives a differential input between a first reception pulse signal, i.e. an internal signal at a secondary winding of a first transformer and a second reception pulse signal, i.e. an internal signal at a secondary winding of a second transformer; a second pulse detector that receives the differential input between the first reception pulse signal and the second reception pulse signal with input polarity reversed to that of the first pulse detector; and a logic unit that generates a reception pulse signal based on output signals of the first and second pulse detectors, respectively.

Systems and methods for voltage compensation based on load conditions in power converters. For example, a system controller for regulating a power converter includes a first controller terminal; a second controller terminal; and a compensation current generator. The compensation current generator is configured to receive an input signal through the first controller terminal. The input signal indicates a first current flowing through a primary winding of a power converter. The compensation current generator is configured to receive a demagnetization signal related to a demagnetization period of the power converter and associated with an auxiliary winding of the power converter. The compensation current generator is configured to generate a compensation current based at least in part on the input signal and the demagnetization signal. The compensation current generator is connected to a resistor. The resistor is configured to generate a compensation voltage based at least in part on the compensation current.

A USB-power delivery integrated circuit controller includes: one or more driver circuits configured to control operation of a buck-boost converter; a regulator configured to regulate an internal supply voltage of the controller from a variable input voltage of the buck-boost converter in a regulation mode, and to pass the variable input voltage as the internal supply voltage without regulation in a bypass mode, the regulator being in the bypass mode when the variable input voltage is below the internal supply voltage, the regulator including an amplifier and a pass transistor configured to pass a current that is inversely proportional to an output of the amplifier; a clamping circuit configured to limit an overdrive voltage of the pass transistor during an inrush current event; and an override circuit configured to deactivate the clamping circuit in the bypass mode when the current passed by the pass transistor is below a current threshold.

A switching method for a half bridge power converter includes at least a pair of power switches in legs of the convertor providing upper and lower branch power switches and first and second gate control circuits for the upper and lower branch power switches. The switching method includes sensing the current derivative in the upper and lower branches during switching of the pair of power switches to provide a first signal and a second signal proportional to the current derivative of the power current in the upper and lower power switches, summing the first and second signals to provide a summed current derivative signal, and adding the summed current derivative signal to the power switch command signal of the first and second gate control circuits causing the summed derivative signals to modulate the gate commutation signals of the gate control circuits.

An auxiliary power circuit of a conversion module is used to supply power to a control unit, and an input end of the conversion module includes an even number of energy storage units coupled in series. The auxiliary power circuit includes an even number of primary-side circuits and a secondary-side circuit. Each primary-side circuit includes a first switch unit, a second switch unit, and a resonance tank. The first switch unit is connected to the second switch unit in series, and is correspondingly connected to one of the energy storage units in parallel. The resonance tank is connected to the second switch unit in parallel. The secondary-side circuit is coupled to the resonance tanks of two of the primary-side circuits to acquire power and supply power to the control unit.

A switched-mode power supply includes a first switch transistor. A drain of the first switch transistor receives an input voltage on a direct current input bus of the switched-mode power supply, and a source is connected to a reference ground. The power supply circuit includes a junction field-effect transistor (JFET), where a drain of the JFET receives the input voltage, a gate is connected to the reference ground, and a source outputs a supply voltage or a supply current. During each switch cycle, the first switch transistor is controlled to be turned off or a drain voltage is controlled to be greater than or equal to a first threshold voltage when the first switch transistor is turned on, such that the supply voltage or the supply current satisfies a drive voltage of the first switch transistor and an operating voltage of a to-be-powered circuit of the switched-mode power supply.