Patent classifications
H02M1/0032
POWER SUPPLY WITH HAYSTACK EFFICIENCY
A power supply may include multiple converters connected in parallel. The power supply may detect a signal that indicates how much power a device uses. Based on the signal, a converter controller may determine which of the multiple converters to activate or deactivate to supply enough power to meet the power load of the device and to operate the highest efficiency possible. The amount of power output from the power supply may be the sum of the power output by each of the converters that is activated. The power supply may use the multiple converters to operate at high efficiency throughout a wide range of power load levels. Such a power supply may achieve a haystack (i.e., near flat) power efficiency curve throughout a large part of its operating range.
DC-DC converter and display device having the same
A DC-DC converter including a first power supply including a first converter outputting a first power voltage, a first sensor detecting a panel current from an output of the first converter; and a first output group including a plurality of inverting converters outputting a second power voltage based on the panel current; a second power supply including a second converter outputting the first power voltage, and a second output group including a plurality of inverting converters outputting the second power voltage based on the panel current; and a first phase controller controlling operations of the inverting converters included in each of the first and second output groups based on the detected panel current. The second power supply operates when the panel current exceeds a predetermined enable value.
Mode operation detection for control of a power converter with an active clamp switch
A primary controller configured for use in a power converter comprising a control circuit configured to determine a mode of operation of the power converter in response to a drive signal of a power switch. The control circuit further configured to generate a control signal in response to a signal representative of the mode of operation of the power converter, wherein the control signal represents a delay time to enable a turn on of the power switch after a turn off of a clamp switch. The control circuit further configured to generate a clamp drive signal to control the clamp switch. The primary controller further comprises a drive circuit configured to generate a drive signal to enable the power switch to transfer energy from an input of the power converter to an output of the power converter.
MANAGEMENT OF VOLTAGE REGULATOR UNITS IN FIELD PROGRAMMABLE ARRAYS
An electronic device has a power rail that is driven by voltage regulators and provides a rail voltage. Each voltage regulator has an output interface electrically coupled to the power rail to deliver up to a predefined regulator current to the power rail. In each voltage regulator, a voltage regulator controller has an input coupled to the output interface by a feedback path and controls a drive path coupled to the output interface. A bypass unit is coupled to the drive path and voltage regulator controller and operates in a standby mode or an operational mode. In the standby mode, the bypass unit bypasses the feedback path and the respective voltage regulator does not deliver current to the power rail, while in the operational mode, the bypass unit does not bypass the feedback path and the respective voltage regulator delivers up to the predefined regulator current to the power rail.
Compensating gain loss for a power converter in DCM and CCM
Various embodiments relate to a current loop controller configured to control a boost converter, including: an amplifier configured to scale a measured current; a subtractor configured to subtract the scaled measured current from a desired current and to output an error signal; a controller including an integral part and a proportional part configured to produce a control signal based upon the difference signal and a gain value, wherein the gain value is based upon a measured value t.sub.ps, wherein t.sub.ps is the on-time plus the secondary time of the boost converter; and a switch signal generator configured to produce a gate signal based upon the control signal, wherein the gate signal controls the boost converter.
Light load mode entry or exit for power converter
During a first mode of operation, a zero current detect (ZCD) signal is asserted in response to detecting a zero current condition at a switch node of a power converter. The power converter enters a light load mode of operation when the ZCD signal is asserted between a beginning point and a trigger point of a period of a PWM signal. A compensator voltage is generated based on a feedback voltage indicative of an output voltage. The compensator voltage is compared to a threshold voltage that represents a limit for the compensator voltage during the light load mode of operation determined over a range of the output voltage. The power converter exits the light load mode back to the first mode of operation in response to the compensator voltage being beyond the threshold voltage.
Configurable-speed multi-phase DC/DC switching converter with hysteresis-less phase shedding and inductor bypass
Some embodiments provide a multi-phase DC/DC switching converter in which each of the phases are controlled using a common comparator for comparing an output voltage of the switching converter and a reference voltage, with in some embodiments each of the phases including a bypass switch for coupling ends of an output inductor of the switching converter. Some embodiments provide a multi-phase DC/DC switching converter in which some of the phases are operated with clock signals having frequencies different than clock signals used for operating others of the phases. Some embodiments provide a multi-phase DC/DC switching converter in which some of the phases include inductors having inductances different than inductances for inductors of others of the phases.
CONTROL CIRCUIT FOR A TOTEM POLE POWER FACTOR CORRECTION CIRCUIT AND THE METHOD THEREOF
A totem pole PFC (Power Factor Correction) circuit, having: a first switch, a second switch and a control circuit. When the totem pole PFC circuit works in CCM (Continuous Current Mode), the control circuit is configured to turn on a main switch when a current detecting signal indicative of an AC input current of the totem pole PFC circuit decreases to a current valley reference signal, and keep the main switch ON for a first on-time period. When the totem pole PFC circuit works in DCM (Discontinuous Current Mode), the control circuit is configured to turn on the main switch at a valley of a switching voltage after expiry of a time delay started from when the AC input current decreases to zero, and keep the main switch ON for a second on-time period.
DYNAMIC POWER MANAGEMENT IN LOW POWER RADAR SOLUTIONS
A system includes a power manager, where the power manager includes a direct current (DC) to DC converter. The DC to DC converter includes a first driver configured to provide a voltage at a first power level. The DC to DC converter also includes a second driver configured to provide the voltage at a second power level, where the second power level is lower than the first power level. The system also includes a radar sensor configured to receive the voltage. The system further includes a controller configured to instruct the power manager to switch between the first driver and the second driver based at least in part on an activity level of the radar sensor.
COMMUNICATION APPARATUS, CONTROL METHOD, AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM STORING PROGRAM
A communication apparatus comprises a shift unit configured to shift, based on a start of processing for connection between the communication apparatus and a predetermined external apparatus supporting authentication processing by a predetermined authentication method using an authentication server in a state in which the communication apparatus operates in a first state in which a processor of the communication apparatus operates at a first operating frequency, the state of the communication apparatus to a second state in which the processor of the communication apparatus operates at a second operating frequency higher than the first operating frequency; and an authentication unit configured to execute authentication by the predetermined authentication method via the predetermined external apparatus in the state in which the communication apparatus operates in the second state.