Adaptive-on-time techniques to improve the frequency variations inherent in constant-on-time COT converters are presented. A switching converter contains a power switch; a pulse generator adapted to generate a pulsed signal to switch the power switch on with a switching frequency; a ramp generator adapted to generate a ramp signal; and a controller adapted to detect a parameter of the ramp signal, compare the parameter with a reference value, and to generate a control signal based on the comparison to control the switching frequency. This allows controlling a switching frequency of the converter without increasing a noise level of the converter.

A switching converter comprising a regulation circuit adapted to regulate an output value of the converter based on a ramp signal is provided. A feedback circuit adapted to control at least one of a delay and a slope of the ramp signal based on a parameter of the ramp signal is also provided. A method of regulating an output value of a switching converter is also presented.

A power converter having a smooth transition control mechanism is provided. An oscillator circuit outputs a clock signal. A control circuit receives the clock signal from the oscillator circuit and outputs a control signal based on the clock signal. A driver circuit outputs a high-side conduction signal and a low-side conduction signal according to the control signal. A high-side switch is turned on or off according to the high-side conduction signal from the driver circuit. A low-side switch is turned on or off according to the low-side conduction signal from the driver circuit. The oscillator circuit receives the high-side conduction signal from the driver circuit. The oscillator circuit, according to the high-side conduction signal, determines whether or not the clock signal outputted to the control circuit needs to be adjusted.

A control circuit includes a timeout circuit configured to receive a first control signal. The timeout circuit asserts a timeout output signal on a timeout circuit output responsive to an expiration of a time period following assertion of the first control signal. A counter circuit has an input coupled to the timeout circuit output and has a counter circuit output. Responsive to assertion of the first control signal, the counter circuit selectively increments an output count value on the counter circuit output responsive to the timeout output signal having a first logic state or decrements the output count value on the counter circuit output responsive to the timeout output signal having a second logic state. A comparator circuit has a control input coupled to the counter circuit output. The comparator circuit adjusts a magnitude of a reference signal responsive to the output count value from the counter circuit.

A deadtime control scheme for improving buck converter light load efficiency.

An external power supply and a system connection detection unit applied thereto are provided. For providing DC power, the external power supply separably connects with a positive input terminal and a negative input terminal of a system through a positive output terminal and a negative output terminal respectively. When the positive output terminal and the negative output terminal are respectively connected to the positive input terminal and the negative input terminal, a system detection terminal connects with a system connection terminal of the system, and a connection status signal generated by the system connection detection unit switches the operation of the external power supply from a deep sleeping mode to a normal operation mode. The system connection terminal is electrically connected to one of the positive input terminal and the negative input terminal through at least a first resistive element.

The present invention provides a power converter, and a control circuit and a standby power saving method thereof. The power converter provides an output voltage from an output terminal through an enable switch circuit to a power receiver. A detection signal shows whether a voltage at a signal transmission pin of the power converter is in a predetermined range, if not, the enable switch circuit is turned OFF. The power converter adjusts a feedback signal according to the detection signal or according to the detection signal and the output voltage, so as to adjust the output voltage to be lower than a normal operation level in a normal operation mode, to save power in a standby mode.

A semiconductor device, for controlling a power supply which generates and outputs a driving pulse, includes: a clock generating circuit with an oscillating circuit in which a frequency can be changed and which generates a clock signal; a voltage/electric current control circuit which provides timing to turn off a switching element; a setting terminal to provide setting information from outside; a switch between a first power supply terminal and a second power supply terminal; and an internal power supply voltage control circuit which controls the switch. When voltage of the setting terminal is lower than a first voltage value, the device advances to a first stop mode in which output of a driving pulse is stopped. When voltage of the setting terminal is higher than the first voltage value, the device advances to a second stop mode in which the output of the driving pulse is stopped.

A power delivery device and a control method are shown. The power delivery device includes a power conversion circuit, a power factor correction circuit, and an output voltage control circuit. The power conversion circuit includes a primary side and a secondary side, and is configured to receive an input voltage and convert the input voltage to an output voltage. The power factor correction circuit is electrically coupled to the primary side and configured to increase the power factor of the power delivery device. The output voltage control circuit is electrically coupled to the secondary side and configured to control the voltage level of the output voltage. When the voltage level of the output voltage is lower than a predetermined level, the power factor correction circuit is deactivated.

An apparatus for delivering power to a load, which comprises an isolated power converter that converts input power on a primary side to output power and a supply voltage at a node on a secondary side. On the secondary side, a load switch is located on a current path to the load. A secondary-side control circuitry controls the load switch to operate in an ON mode in which current is provided to the load, and in response to a fault condition corresponding to an effective sudden disconnection of the supply voltage, switches the load switch into an OFF mode in which the current path to the load is blocked.