A power semiconductor module includes a semiconductor switching element, a gate control pattern to which a gate electrode of the semiconductor switching element is connected, a source control pattern to which a source electrode of the semiconductor switching element is connected, a capacitor to form a low-pass filter, a capacitor arrangement pattern to which one end of the capacitor is connected, and a wire. The other end of the capacitor is connected to the source control pattern. The wire electrically connects the capacitor arrangement pattern and the gate control pattern.

One or more embodiments can comprise a method, including detecting, by a power converter comprising a processor, a feedback signal level based on based on an output condition of an error amplifier. The method can further comprise, based on the feedback signal level, setting, by the power converter, a combination of a switching frequency and a magnetizing current level, wherein the combination is selected to achieve an electromagnetic interference (EMI) level for the power converter that satisfies a first condition.

A power circuit is provided that includes at least a first power supply unit and a second power supply unit. The first power supply unit includes a first input section, a first AC voltage generator, a first rectification-and-smoothing section, and a first isolation section that is provided between the first AC voltage generator and the first rectification-and-smoothing section. The second power supply unit includes a second input section, a second AC voltage generator, a second rectification-and-smoothing section, and a second isolation section that is provided between the second AC voltage generator and the second rectification-and-smoothing section. The power circuit is configured such that the second AC voltage generator generates an AC voltage having a phase obtained by inverting a phase of the AC voltage generated by the first AC voltage generator.

An amplifier system may include at least one input source, a flyback converter including a pair of complementary metal oxide silicon field effect transistor (MOSFETs), a controller integrated circuit (IC) having a quasi-resonant (QR) pin and configured to provide a biased drive current to the flyback converter, and a transition component arranged at the controller IC and configured to correct pulse width modulation at the IC to ensure the voltage at a transition pin of the IC is above a predefined threshold during a resonant transition.

The disclosed embodiments provide a system that operates a flyback converter. During activation of a synchronous rectifier (SR) controller on a secondary side of the power converter, the system temporarily disables driving of a gate of a metal-oxide-semiconductor field-effect transistor (MOSFET) by the SR controller to enable synchronization of the SR controller to a switching frequency on a primary side of the power converter. After driving of the gate of the MOSFET by the SR controller has been disabled for a pre-specified period, the system enables driving of the gate of the MOSFET by the SR controller.

A system includes a current mirror coupled to a first transistor, the first transistor includes a first gate, a first current terminal, and a second current terminal, a controller coupled to the current mirror and a converter, the controller is to output a delayed signal for a second transistor, the second transistor being a part of the converter, and a source voltage coupled to the current mirror.

Provided is a driving apparatus that drives a switching device, the driving apparatus including a reference potential line, a first switching control unit configured to switch whether to connect a control terminal of the switching device to the reference potential line, a first resistor element arranged in series to the first switching control unit in a path from the control terminal of the switching device to the reference potential line, a first capacitor provided in parallel with the first resistor element in the path from the control terminal of the switching device to the reference potential line, and a discharge control unit configured to control whether to discharge the first capacitor.

In at least some examples, an apparatus includes a logic circuit, first transistor, and second transistor. The logic circuit has a first logic circuit output, and a second logic circuit output. The first transistor has a first transistor gate, a first transistor source, and a first transistor drain, the first transistor gate coupled to the first logic circuit output, the first transistor drain adapted to couple to a voltage source, and the first transistor source coupled to a switching terminal. The second transistor has a second transistor gate, a second transistor source, and a second transistor drain, the second transistor gate coupled to the second logic circuit output, the second transistor drain adapted to couple to the voltage source, and the second transistor source coupled to the switching terminal, wherein a transistor width of the second transistor is larger than a transistor width of the first transistor.

A control circuit for a power converter comprising switching transistors and an output inductor is disclosed. One terminal of the output inductor serves as an output node, and another terminal of the output inductor serves as a switching node. The control circuit is configured to generate a control signal for controlling switching transistors in the power converter. The control circuit includes: a RC oscillator network connected to two terminals of the output inductor, the RC oscillator network configured to generate an oscillation signal containing a feedback ramp slope compensation component in response to a change in a voltage across the terminals of the output inductor; a comparator; an on-time generation circuit; and a control signal generation circuit to generate the control signal for controlling the switching transistors in the power converter.

A radiation tolerant gate driver for power converters with active-clamp reset and active-driven synchronous rectification uses integrated logic drivers for high efficiency and wide input range. A keep alive circuit prevents power train transistors from remaining on for extended durations after a transient or an undervoltage lockout (UVLO) event. Each of the integrated logic drivers includes two gate driver circuits, where one of the gate driver circuits uses the output of the other of the gate driver circuits as input per a logic table of the integrated logic driver, to ensure no shoot-through when the respective power train transistors are turned on and off.