A control signal generator includes an error amplifier, a first comparator, a second comparator, a logic circuit and a pulse generator. The error amplifier has a first output, a first input, a second input and a first snooze input. The first comparator has a second output, a third input and a fourth input. The third input is coupled to the first output. The second comparator has a third output, a fifth input, a sixth input and a second snooze input. The fifth input is coupled to the third input. The logic circuit has a fourth output and logic circuit inputs, including a first logic circuit input coupled to the second output. The pulse generator has a fifth output and a seventh input. The seventh input is coupled to the fourth output. A snooze mode controller has a sixth output coupled to the first snooze input and the second snooze input.

DC-DC power converter control comprises current starved delay lines for phase shifting control signals that set and reset a RS flip-flop to provide controllable PWM pulse widths from narrow to wide at a clock frequency. Precise pulse width control and a guaranteed minimum pulse width for pulse frequency modulation (PFM) control the DC-DC power converter during low power demand is also provided. PFM control maintains the same pulse width while decreasing the number of pulses per second when the output voltage exceeds an upper value and increases the number of pulses per second when the output voltage is less than a lower value. Voltage-to-current converters provide control currents to the current starved delay lines that provide the control signals to the SET and RESET inputs of the RS flip-flop. A D-flip-flop may further be used to improved circuit operation when generating high duty cycle (>50 percent) pulse widths.

In a described example, a circuit includes a mode control circuit having an input and a mode control output. The mode control output is adapted to be coupled to a mode input of a DC-to-DC power converter. The mode control circuit is configured to provide a mode control signal at the mode control output. The mode control signal has a frequency and a duty cycle for causing the power converter to operate within an inaudible frequency range by transitioning the power converter between a power save mode and a pulse width modulation (PWM) mode. The mode control circuit is configured to control the duty cycle responsive to the input of the mode control circuit.

A multi-phase voltage converter has a plurality of integrated circuits (ICs), and a controller. Each IC has a power switch, a monitoring pin and a current sense pin. The power switch is controlled to convert an input voltage to an output voltage. The current sense pin is capable of providing a current sense signal representative of a current flowing through the power switch. The controller is capable of providing a clock signal via the monitoring pin, and provides a plurality of data signals via the current sense pin of the plurality of ICs. Each of the plurality of ICs is assigned an identification code based on the clock signal and one of the plurality of data signals.

An ultra-low-power mode control circuit for a power converter includes four modules: a level shift circuit, a start circuit, a static clamp circuit, and a control circuit. When a chip is powered on and a core voltage has not been established, the control circuit firstly starts a power source built-in clock to support operation of the power converter. When the core voltage is established, the control circuit determines whether to switch to an external clock according to a level of a mode selection signal. After the core voltage is powered down, the control circuit automatically wakes up the built-in clock to work.

Disclosed in the present invention are a charge pump circuit, a chip, and a communication terminal. The charge pump circuit comprises a phase clock generation module, an acceleration response control module, and a plurality of sub charge pump modules. By generating a plurality of clock signals with a fixed phase difference by means of the phase clock generation module, correspondingly controlling the plurality of sub charge pump modules to generate output voltages, and by means of the acceleration response control module, measuring the output voltage of each sub charge pump module, and separately outputting a logic signal to the phase clock generation module and each sub charge pump module, the frequency of the clock signals outputted by the phase clock generation module is changed, and the charge and discharge time of a capacitor in each sub charge pump module is reduced.

A power converter and a control method thereof are provided. The power converter includes a primary side switching circuit, a secondary side switching circuit, a transformer, and a control circuit. The primary side switching circuit includes a first set of switches. The secondary side switching circuit includes a second set of switches. The transformer is coupled between the primary side switching circuit and the secondary side switching circuit. The control circuit is configured to control power transfer between the primary side switching circuit and the secondary side switching circuit by controlling the first and second sets of switches. The control circuit is adapted to enable and disable the first and second sets of switches in an enabling duration and a disabling duration respectively and alternatively.

A converter system includes a first switch and a controller configured to switch the first switch between first and second states based on input and output voltages of the converter system, wherein the controller includes: a timer unit including a first timer configured to determine a first duration based on a target switching frequency of the converter system, and a second timer configured to determine a second duration based on a predetermined duration equal to or greater than a minimum duration of the first state of the first switch and the input and output voltages; and a control logic unit, configured to switch the first switch from the second state to the first state upon expiration of both the first and second durations.

A power converter and a control method thereof are provided. The power converter includes a primary side switching circuit, a secondary side switching circuit, a transformer, and a control circuit. The primary side switching circuit includes a first set of switches. The secondary side switching circuit includes a second set of switches. The transformer is coupled between the primary side switching circuit and the secondary side switching circuit. The control circuit is configured to control power transfer between the primary side switching circuit and the secondary side switching circuit by controlling the first and second sets of switches. The control circuit is adapted to enable and disable the first and second sets of switches in an enabling duration and a disabling duration respectively and alternatively.

A controller for controlling a DC-DC converter in a discontinuous conduction mode (DCM) includes an output module configured to provide a switch control signal to the DC-DC converter having an on-time and a switching frequency. The controller includes an on-time-control-module configured to receive a first compensation signal based on the output voltage of the DC-DC converter; and set the on-time of the switch control signal based on the first compensation signal. The controller also includes a frequency-control-module configured to receive a second compensation signal, wherein the second compensation signal is based on the output voltage of the DC-DC converter, and regulate the second compensation signal to a target range by setting the switching frequency of the switch control signal to one of a plurality of pre-defined discrete switching frequencies.