The invention comprises a method for manufacturing an inductor, comprising the steps of: casting a cast winding comprising an inner cavity; inserting a first inductor core subsection into the inner cavity; inserting a second inductor core subsection into the inner cavity; and mechanically coupling the first inductor core subsection to the second inductor core subsection to form an inductor core wound by the cast windings. The method of manufacturing optionally includes the steps of: forming at least a portion of the cast winding into an arced helical shape; forming the first inductor core subsection and the second inductor core subsection into elements of a torpid shaped inductor core; deforming the cast winding to physically allow the step of inserting the first inductor core subsection into the inner cavity; and/or deforming at least a portion of the cast winding into an arced helical coil shape after the step of inserting.

A power converting apparatus includes: a reactor including a first end and a second end, the first end being connected to an alternating-current power supply; a rectifier circuit connected to the second end of the reactor and including at least one switching element, the rectifier circuit converting an alternating-current voltage output from the alternating-current power supply into a direct-current voltage; and a detecting unit that detects a physical quantity indicating an operation state of the rectifier circuit, wherein the number of times of switching of the switching element is changed depending on the operation of the rectifier circuit.

A capacitor module includes a smoothing capacitor, a P-side Y capacitor and a N-side Y capacitor as noise absorbing capacitors, a capacitor case, a P-side bus bar, a N-side bus bar, and a ground bus bar. A virtual plane along a P-side electrode surface, which is an electrode surface on a high potential side of the smoothing capacitor, is referred to as a P-side virtual plane. A virtual plane along a N-side electrode surface, which is an electrode surface on a low potential side of the smoothing capacitor, is referred to as a N-side virtual plane. A region between the P-side virtual plane and the N-side virtual plane is defined as a PN region. The entire noise absorbing capacitor and the entire ground bus bar are arranged in the PN region.

A power filtration system filters out a common mode signal from a DC conductor of a power system. The power filtration system comprises a first filter and at least one of a load or a power circuit. The first filter is connected to the DC conductor and configured to pass the common mode signal. The load is configured to dissipate the energy of the common mode signal. The power circuit is configured to conduct the common mode signal to an energy storage device.

A voltage generated in a DC line at the time when a sub module is deactivated in the event of a short-circuiting fault in the DC line is suppressed. A power conversion system includes a power converter including a leg circuit, a control device, and a voltage suppression circuit connected to a DC line. The leg circuit includes a plurality of sub modules connected in series, and at least one of them is a first sub module implemented by a sub module in a full-bridge configuration or a 1.5 half-bridge configuration. When the control device detects a short-circuiting fault in the DC line, it stops a switching operation of the plurality of sub modules. The voltage suppression circuit is configured to suppress a voltage generated in the DC line when the switching operation is stopped.

A totem-pole PFC circuit is provided. The totem-pole PFC circuit includes an inductor, a first bridge arm and a second bridge arm. The first bridge arm includes a first switch and a second switch connected in series. A first middle node connected between the first and second switches is coupled to a first terminal of an AC power source through the inductor. The second bridge arm connected to the first bridge arm in parallel includes a third switch and a fourth switch connected in series. A second middle node connected between the third and fourth switches is coupled to a second terminal of the AC power source. When a polarity of the AC power source is changed, a change time of a voltage on the second middle node is longer than a preset time not less than 20 μs.

A system may be provided that includes an energy storage device, and an inverter electrically coupled to the energy storage device. The system also includes a passive filter electrically coupled between the energy storage device and the inverter. The passive filter includes a first coupled-inductor and at least one first bypass capacitor. The first coupled-inductor includes at least two magnetically coupled windings. The passive filter is configured to reduce or eliminate alternating current at the energy storage device.

The present invention relates to an electrical system comprising at least one magnetic cell connected to an external grid system and comprising a filtering cell having a capacitor X (CDM1, CDM2, CDM3) and a capacitor Y (CY). Said electrical system comprises an array of switches, connected up-circuit of the capacitors X (CDM1, CDM2, CDM3) and Y (CY) of said filtering cell, said array of switches being configured such that: in a single-phase operating mode, the series-connected switches (S2, S3) on the unpowered phases (B, C) are open, and the switches (S1, S4) connected between the first phase (A) and the other phases (B, C) are closed; in a multi-phase operating mode, the series-connected switches (S2, S3) are closed and the switches (S1, S4) connected between the first phase (A) and the other phases (B, C) are open.

In a described example, a circuit includes a sensor, a controller and an amplifier. The sensor has a sensor input and a sensor output. The sensor input is adapted to be coupled to a chassis of a switch-mode power supply (SMPS). The controller has an input, a timing output and a level output. The input of the control circuit is coupled to the sensor output. The amplifier has a timing control input, a level control input and an amplifier output. The level control input is coupled to the level output of the controller. The timing control input is coupled to the timing output, and the amplifier output is coupled to the sensor input. The amplifier is configured to provide compensation pulses at the amplifier output having magnitude and timing to reduce common-mode noise on the chassis.

A circuit arrangement comprises: a primary coil and a secondary coil, which are inductively coupled, but galvanically isolated from one another; a first voltage divider which is connected between a first terminal and a second terminal of the secondary coil and which has a center tap connected to a ground node; a second voltage divider, which is connected between the first terminal and the second terminal of the secondary coil; and an active circuit, which is connected to the first terminal and the second terminal of the secondary coil, a center tap of the second voltage divider and to the ground node. The active circuit is configured to provide a current path between the first terminal of the secondary coil and the ground node and between the second terminal of the secondary coil and the ground node depending on a voltage at the center tap of the second voltage divider.