A control system for a DC-DC voltage converter includes a microcontroller having first and second applications. The first application commands the microcontroller to generate a first signal that is received at a first pin on a high side integrated circuit to transition a first plurality of FET switches to an open operational state, and that is received at a first pin on the low side integrated circuit to transition a second plurality of FET switches to the open operational state. The second application commands the microcontroller to generate a second signal that is received at a second pin on the high side integrated circuit to transition the first plurality of FET switches to the open operational state, and that is received at a second pin on the low side integrated circuit to transition the second plurality of FET switches to the open operational state.

In one embodiment, a control circuit configured to control a power stage circuit of a primary-controlled flyback converter, can include: (i) a current sense circuit that generates a current sense signal by sampling a primary current; (ii) a voltage sense circuit that generates a voltage sense signal by sampling an auxiliary voltage after a blanking time has elapsed; (iii) a control signal generator that generates a switch control signal according to the voltage sense signal and the current sense signal; and (iv) the switch control signal being configured to control a power switch of the power stage circuit, where the switch control signal is active during a constant on time.

A power management integrated circuit (PMIC) may have a loop controller configured to receive a first error signal from a first driver IC having a first driver powered from a supply voltage and configured to drive a first output signal responsive to a first input signal and a first error detector configured to generate the first error signal based between the supply voltage as detected locally to the first driver IC and a first reference voltage associated with the first driver, receive a second error signal from a second driver IC analogous to the first driver IC, and regulate the supply voltage based on the first and second error signals.

A power management integrated circuit (PMIC) may have a loop controller configured to receive a first error signal from a first driver IC having a first driver powered from a supply voltage and configured to drive a first output signal responsive to a first input signal and a first error detector configured to generate the first error signal based between the supply voltage as detected locally to the first driver IC and a first reference voltage associated with the first driver, receive a second error signal from a second driver IC analogous to the first driver IC, and regulate the supply voltage based on the first and second error signals.

An apparatus includes a first differential pair having a first transistor and a second transistor, wherein a gate of the first transistor is configured to receive a first current sensing signal, and a gate of the second transistor is configured to receive a second current sensing signal, a second differential pair having a third transistor and a fourth transistor, wherein a gate of the third transistor is configured to receive a predetermined reference, and a gate of the fourth transistor is connected to a capacitor, and a high gain stage comprising a first leg and a second leg, wherein a first node of the first leg is connected to a drain of the first transistor and a drain of the fourth transistor, and a second node of the second leg is connected to a drain of the second transistor and a drain of the third transistor.

An apparatus includes a first differential pair having a first transistor and a second transistor, wherein a gate of the first transistor is configured to receive a first current sensing signal, and a gate of the second transistor is configured to receive a second current sensing signal, a second differential pair having a third transistor and a fourth transistor, wherein a gate of the third transistor is configured to receive a predetermined reference, and a gate of the fourth transistor is connected to a capacitor, and a high gain stage comprising a first leg and a second leg, wherein a first node of the first leg is connected to a drain of the first transistor and a drain of the fourth transistor, and a second node of the second leg is connected to a drain of the second transistor and a drain of the third transistor.

A power converter includes an isolator having a first terminal, a second terminal, a third terminal, and a fourth terminal. A first circuit has a first terminal coupled to the first terminal of the isolator and has a second terminal coupled to the second terminal of the isolator. A second circuit has a first terminal coupled to the third terminal of the isolator and has a second terminal coupled to the fourth terminal of the isolator. The second circuit includes a controller configured to transmit a control signal through the isolator to the first circuit. The control signal includes a first indication to turn on power transmission through the isolator from the first circuit to the second circuit, a second indication of a status, and a third indication to turn off power transmission.

A power converter includes an isolator having a first terminal, a second terminal, a third terminal, and a fourth terminal. A first circuit has a first terminal coupled to the first terminal of the isolator and has a second terminal coupled to the second terminal of the isolator. A second circuit has a first terminal coupled to the third terminal of the isolator and has a second terminal coupled to the fourth terminal of the isolator. The second circuit includes a controller configured to transmit a control signal through the isolator to the first circuit. The control signal includes a first indication to turn on power transmission through the isolator from the first circuit to the second circuit, a second indication of a status, and a third indication to turn off power transmission.

There is provided a power saving and highly reliable semiconductor device on which a switching power supply circuit and a driver circuit are mounted together, and which can perform appropriate control by the driver circuit even when a battery terminal is disconnected while reducing power loss in the entire semiconductor device. The semiconductor device includes: a first terminal which is connected to a battery power source; a switching power supply circuit which steps down a battery voltage input from the first terminal; a second terminal which is connected to a switching power source different from the battery power source; a regulator circuit which steps down a voltage input from the second terminal; and a predriver circuit which is connected to the regulator circuit.

There is provided a power saving and highly reliable semiconductor device on which a switching power supply circuit and a driver circuit are mounted together, and which can perform appropriate control by the driver circuit even when a battery terminal is disconnected while reducing power loss in the entire semiconductor device. The semiconductor device includes: a first terminal which is connected to a battery power source; a switching power supply circuit which steps down a battery voltage input from the first terminal; a second terminal which is connected to a switching power source different from the battery power source; a regulator circuit which steps down a voltage input from the second terminal; and a predriver circuit which is connected to the regulator circuit.