An oscillation circuit includes first and second constant current circuits, first and second switch circuits, first and second MOS transistors, and an output port. The first constant current circuit is connected to one port of a capacitor. The first MOS transistor has a gate and a drain connected to the second constant current circuit and a source connected to another port of the capacitor. The second MOS transistor has a gate connected to the gate of the first MOS transistor, and a drain connected to the one port of the capacitor. The second switch circuit is connected between a source of the second MOS transistor and a second power supply terminal. The output port outputs a signal based on a voltage of the one port. Turn-on and turn-off of the first and second switch circuits are controlled by the signal of the output port and an inverted signal.

Relaxation oscillator and method for providing an output frequency. For example, the relaxation oscillator includes a reference generator, a capacitor, a first comparator, a second comparator, a latch, and a temperature compensation circuit. The reference generator is configured to generate a first bias current, a first bias voltage and a second bias voltage. The capacitor is configured to be charged by a charging current to generate a charged voltage, and the charging current is generated based on at least the first bias current. The first comparator is configured to compare the charged voltage and the first bias voltage to generate a first comparison result, and the second comparator is configured to compare the charged voltage and the second bias voltage to generate a second comparison result. The latch is configured to generate a clock signal based on at least the first comparison result and the second comparison result.

A sensor interface circuit includes: an RF switch having a control node; a bias circuit electrically connected to the control node and applying, to the control node, a voltage at a first level or a second level corresponding to a linear region of a reflection characteristic; a first variable oscillation circuit electrically connectable to a first sensor; a second variable oscillation circuit electrically connectable to a second sensor; and a difference circuit electrically connected between the first variable oscillation circuit and the bias circuit, and between the second variable oscillation circuit and the bias circuit.

A sensor interface circuit includes: an RF switch having a control node; a bias circuit electrically connected to the control node and applying, to the control node, a voltage at a first level or a second level corresponding to a linear region of a reflection characteristic; a first variable oscillation circuit electrically connectable to a first sensor; a second variable oscillation circuit electrically connectable to a second sensor; and a difference circuit electrically connected between the first variable oscillation circuit and the bias circuit, and between the second variable oscillation circuit and the bias circuit.

Disclosed is a semiconductor device that suppresses stress-induced resistance value changes. The semiconductor device includes a resistance correction circuit. The resistance correction circuit includes a first resistor whose stress-resistance value relationship is a first relationship, a second resistor whose stress-resistance value relationship is a second relationship, and a correction section that controls the resistance value of a correction target resistor. The correction section detects the difference between the resistance value of the first resistor and the resistance value of the second resistor and corrects, in accordance with the result of detection, the resistance value of the correction target resistor.

Disclosed is a semiconductor device that suppresses stress-induced resistance value changes. The semiconductor device includes a resistance correction circuit. The resistance correction circuit includes a first resistor whose stress-resistance value relationship is a first relationship, a second resistor whose stress-resistance value relationship is a second relationship, and a correction section that controls the resistance value of a correction target resistor. The correction section detects the difference between the resistance value of the first resistor and the resistance value of the second resistor and corrects, in accordance with the result of detection, the resistance value of the correction target resistor.

A varactor is described that may be constructed in CMOS and has a high tuning range. In some embodiments, the varactor includes a well, a plurality of gates formed over the well and having a capacitive connection to the well, the gates comprising a first subset of the gates that are adjacent and consecutive and coupled to a positive pole of an excitation oscillation signal, and a second subset of the gates that are adjacent and consecutive and coupled to a negative pole of the excitation oscillation signal, and a plurality of source/drain terminals formed over the well and having an ohmic connection to the well, each coupled to a respective gate to receive a control voltage to control the capacitance of the varactor.

A stress compensated oscillator circuitry comprises a sensor arrangement for providing a sensor output signal S.sub.Sensor, wherein the sensor output signal S.sub.Sensor is based on an instantaneous stress or strain component a in the semiconductor substrate, a processing arrangement for processing the sensor output signal S.sub.Sensor and providing a control signal S.sub.Control depending on the instantaneous stress or strain component σ in the semiconductor substrate, and an oscillator arrangement for providing an oscillator output signal S.sub.osc having an oscillator frequency f.sub.osc based on the control signal S.sub.Control, wherein the control signal S.sub.Control controls the oscillator output signal S.sub.osc, and wherein the control signal S.sub.Control reduces the influence of the instantaneous stress or strain component σ in the semiconductor substrate onto the oscillator output signal S.sub.osc, so that the oscillator circuitry provides a stress compensated oscillator output signal.

A stress compensated oscillator circuitry comprises a sensor arrangement for providing a sensor output signal S.sub.Sensor, wherein the sensor output signal S.sub.Sensor is based on an instantaneous stress or strain component a in the semiconductor substrate, a processing arrangement for processing the sensor output signal S.sub.Sensor and providing a control signal S.sub.Control depending on the instantaneous stress or strain component σ in the semiconductor substrate, and an oscillator arrangement for providing an oscillator output signal S.sub.osc having an oscillator frequency f.sub.osc based on the control signal S.sub.Control, wherein the control signal S.sub.Control controls the oscillator output signal S.sub.osc, and wherein the control signal S.sub.Control reduces the influence of the instantaneous stress or strain component σ in the semiconductor substrate onto the oscillator output signal S.sub.osc, so that the oscillator circuitry provides a stress compensated oscillator output signal.

A technique for reducing jitter in an oscillating signal generated by an oscillator circuit includes reducing feedback of gate leakage current while increasing electrostatic discharge protection and reducing regulated power supply requirements of the oscillator circuit, as compared to conventional oscillator circuits. A circuit includes a first integrated circuit terminal and a thick gate native transistor of a first conductivity type having a first gate terminal having a first gate thickness. The first gate terminal is coupled to the first integrated circuit terminal. The thick gate native transistor has a first threshold voltage. The thick gate native transistor is configured as a source follower. The circuit includes a second transistor of the first conductivity type having a second gate terminal with a second gate thickness less than the first gate thickness. The second gate terminal is coupled to a source terminal of the thick gate native transistor.