Embodiments of methods and semiconductor devices are described that are configured to determine a negative resistance margin (NRM) of an oscillator circuit. The semiconductor device may include an integrated circuit including an amplifier circuit coupled between a first node and a second node and NRM test circuitry including a resistor circuit selectively coupled between a first contact pad and the first node. The integrated circuit may receive an oscillating signal from an oscillator circuit coupled to the first contact pad and a second contact pad of the integrated circuit. In an NRM test mode, a resistance of the resistor circuit is selectively varied from an initial resistance value to one or more second resistance values and the oscillating signal is monitored at the second node to determine the NRM based on the one or more second resistance values when an amplitude of the oscillating signal falls below a threshold amplitude.

Embodiments of methods and semiconductor devices are described that are configured to determine a negative resistance margin (NRM) of an oscillator circuit. The semiconductor device may include an integrated circuit including an amplifier circuit coupled between a first node and a second node and NRM test circuitry including a resistor circuit selectively coupled between a first contact pad and the first node. The integrated circuit may receive an oscillating signal from an oscillator circuit coupled to the first contact pad and a second contact pad of the integrated circuit. In an NRM test mode, a resistance of the resistor circuit is selectively varied from an initial resistance value to one or more second resistance values and the oscillating signal is monitored at the second node to determine the NRM based on the one or more second resistance values when an amplitude of the oscillating signal falls below a threshold amplitude.

Embodiments of methods and semiconductor devices are described that are configured to determine a negative resistance margin (NRM) of an oscillator circuit. The semiconductor device may include an integrated circuit including an amplifier circuit coupled between a first node and a second node and NRM test circuitry including a resistor circuit selectively coupled between a first contact pad and the first node. The integrated circuit may receive an oscillating signal from an oscillator circuit coupled to the first contact pad and a second contact pad of the integrated circuit. In an NRM test mode, a resistance of the resistor circuit is selectively varied from an initial resistance value to one or more second resistance values and the oscillating signal is monitored at the second node to determine the NRM based on the one or more second resistance values when an amplitude of the oscillating signal falls below a threshold amplitude.

Embodiments of methods and semiconductor devices are described that are configured to determine a negative resistance margin (NRM) of an oscillator circuit. The semiconductor device may include an integrated circuit including an amplifier circuit coupled between a first node and a second node and NRM test circuitry including a resistor circuit selectively coupled between a first contact pad and the first node. The integrated circuit may receive an oscillating signal from an oscillator circuit coupled to the first contact pad and a second contact pad of the integrated circuit. In an NRM test mode, a resistance of the resistor circuit is selectively varied from an initial resistance value to one or more second resistance values and the oscillating signal is monitored at the second node to determine the NRM based on the one or more second resistance values when an amplitude of the oscillating signal falls below a threshold amplitude.