A frequency doubler is provided that filters an input signal to form I and Q components responsive to a tuning signal. A single sideband mixer mixes the I and Q components with I and Q components of a local oscillator signal to form an output signal having a frequency of twice the frequency of the input signal.

A frequency doubler is provided that filters an input signal to form I and Q components responsive to a tuning signal. A single sideband mixer mixes the I and Q components with I and Q components of a local oscillator signal to form an output signal having a frequency of twice the frequency of the input signal.

The present disclosure relates to a pre-5.sup.th-Generation (5G) or 5G communication system to be provided for supporting higher data rates beyond 4.sup.th-Generation (4G) communication system such as long-term evolution (LTE). According to various embodiments of the present disclosure, an apparatus of a transmitter in a wireless communication system may include an oscillating circuit for providing an oscillating signal, and a radio frequency (RF) circuit for converting a frequency of a transmit signal using the oscillating signal, and transmitting the transmit signal. The oscillating circuit may generate a base oscillating signal of a differential signal form, by multiplying a first signal and a second signal which constitute the different signal, generate a first signal set from the first signal and a second signal set from the second signal, and generate a signal in which at least one harmonic component adjacent to an intended frequency component is suppressed using the first signal set and the second signal set.

A multiphase signal generator includes an input port. Furthermore, the multiphase signal generator includes a plurality of phase shifters. Each phase shifter of the plurality of phase shifters is configured to provide an identical phase shift Δφ. At least one phase shifter is connected to the input port. Furthermore, the multiphase signal generator includes a first phase interpolator and at least a second phase interpolator. Each phase interpolator has a respective output terminal. Each phase interpolator is configured to weight a phase of a signal at a respective first input terminal of the phase interpolator with a respective first weighting factor w.sub.i,1 and to weight a phase of another signal at a respective second input terminal of the phase interpolator with a respective second weighting factor w.sub.i,2 to generate an interpolated phase signal at the respective output terminal of the phase interpolator. A first subset of the plurality of phase shifters includes n>1 serially connected phase shifters. The first subset of phase shifters is coupled between the first input terminal and the second input terminal of the first phase interpolator. A different second subset of the plurality of phase shifters includes n serially connected phase shifters. The second subset of phase shifters is coupled between the first input terminal and the second input terminal of the second phase interpolator.

Radio frequency (RF) mixer circuits having a complementary frequency multiplier module that requires no balun to multiply a lower frequency base oscillator signal to a higher frequency local oscillator (LO) signal, and which has a significantly reduced IC area compared to balun-based frequency multipliers. In one embodiment, the complementary frequency multiplier module includes a complementary pair of FETs controlled by an applied base oscillator signal. The complementary FETs are coupled to a common-gate FET amplifier and alternate becoming conductive in response to the base oscillator signal. The alternating switching of the complementary FETs in response to the opposing phases of the base oscillator signal cause the common-gate FET amplifier to output a higher frequency local oscillator (LO) signal. The LO signal is coupled to the LO input of a mixer or mixer core of a type suitable for use in conjunction with a frequency multiplier.

A method and apparatus for controlling a frequency range of a self-resonant frequency (SRF) of a high speed divider implemented in current mode logic (CML) D triggers by controlling a field effect transistor (FET) load resistor bias voltage to FETs operating in linear regions in load resistors in the CML D triggers. Tail currents of the CML D triggers are controlled to track inversely to a resistor value.

An integrated circuit includes a semiconductor substrate and a plurality of circuit elements in or on the substrate. The circuit elements are defined by standard layout cells selected from a cell library. The circuit elements including a plurality of flip-flops. Each flip-flop has a data input terminal, a data output terminal, a clock input terminal, and a clock output terminal. A first one of the flip-flops directly abuts a second flip-flop such that the clock output terminal of the first flip-flop electrically connects with the clock input terminal of the second flip-flop.

An embodiment integrated electronic device comprises a mixer module including a voltage/current transconductor stage including first transistors and connected to a mixing stage including second transistors, wherein the mixing stage includes a resistive degeneration circuit connected to the sources of the second transistors and a calibration input connected to the gates of the second transistors and intended to receive an adjustable calibration voltage, and the sources of the first transistors are directly connected to a cold power supply point.

Networks of superharmonic injection-locked (SHIL) electronic oscillators can be used to emulate Ising machines for solving difficult computational problems. The oscillators can be simulated or implemented in hardware (e.g., with LC oscillators) and are coupled to each other with links whose connection strengths are weighted according to the problem being solved. The oscillators' phases may be measured with respect to reference signal(s) from one or more reference oscillators, each of which emits a reference signal but does not receive input from any other oscillator. Sparsely connected networks of SHIL oscillators and reference oscillators can be used as Viterbi decoders that do not suffer from the information bottleneck between logic computational blocks and memory in digital computing systems. Sparsely connected networks of SHIL oscillators and reference oscillators can also be programmed to act as Boolean logic gates that operate in both forward and backward directions, enabling multipliers that can factor numbers.

Networks of superharmonic injection-locked (SHIL) electronic oscillators can be used to emulate Ising machines for solving difficult computational problems. The oscillators can be simulated or implemented in hardware (e.g., with LC oscillators) and are coupled to each other with links whose connection strengths are weighted according to the problem being solved. The oscillators' phases may be measured with respect to reference signal(s) from one or more reference oscillators, each of which emits a reference signal but does not receive input from any other oscillator. Sparsely connected networks of SHIL oscillators and reference oscillators can be used as Viterbi decoders that do not suffer from the information bottleneck between logic computational blocks and memory in digital computing systems. Sparsely connected networks of SHIL oscillators and reference oscillators can also be programmed to act as Boolean logic gates that operate in both forward and backward directions, enabling multipliers that can factor numbers.