An integrated frequency quadruplet consists of a pair of balanced frequency doublers that are driven in phase quadrature using a hybrid coupler. This approach results, effectively, in a unilateral multiplier that presents a match to the input-driving source, irrespective of the impedance of the doubler stages. The present invention applies this architecture to implement an integrated frequency quadruplet with output frequency of 160 GHz using quasi vertical GaAs varactors fabricated on thin silicon support membranes. The quadruplet has a balanced circuit architecture that addresses degradation issues often arising from impedance mis-matches between multiplier stages. A unique quasi-vertical diode process is used to implement the quadruplet, resulting in an integrated drop-in chip module that incorporates 18 varactors, matching networks and beamleads for mounting. The chip is tailored to fit a multiplier waveguide housing resulting in high reproducibility and consistency in manufacture and performance.

An integrated frequency quadruplet consists of a pair of balanced frequency doublers that are driven in phase quadrature using a hybrid coupler. This approach results, effectively, in a unilateral multiplier that presents a match to the input-driving source, irrespective of the impedance of the doubler stages. The present invention applies this architecture to implement an integrated frequency quadruplet with output frequency of 160 GHz using quasi vertical GaAs varactors fabricated on thin silicon support membranes. The quadruplet has a balanced circuit architecture that addresses degradation issues often arising from impedance mis-matches between multiplier stages. A unique quasi-vertical diode process is used to implement the quadruplet, resulting in an integrated drop-in chip module that incorporates 18 varactors, matching networks and beamleads for mounting. The chip is tailored to fit a multiplier waveguide housing resulting in high reproducibility and consistency in manufacture and performance.

Various NLTL frequency comb generator embodiments are disclosed for compressing rise time, fall time, or both rise time and fall time of an input signal to generate an output signal comprising multiple harmonics of the input signal. The NLTL frequency comb generator may comprise a plurality of segments cascaded in series with each segment comprising a series inductor, a shunt capacitor, and a reverse shunt capacitor for balanced signal compression. The shunt capacitor and the reverse shunt capacitor may be varactors or Schottky diodes that have voltage-dependent capacitance. As a result, both rise time and fall time of the input signal are compressed along the NLTL frequency comb generator. With a sinusoidal signal input, the output signal may be close to a square wave. Such a square wave output naturally suppresses all even harmonics, which can be valuable for odd harmonics signal extraction or filtration.

Various NLTL frequency comb generator embodiments are disclosed for compressing rise time, fall time, or both rise time and fall time of an input signal to generate an output signal comprising multiple harmonics of the input signal. The NLTL frequency comb generator may comprise a plurality of segments cascaded in series with each segment comprising a series inductor, a shunt capacitor, and a reverse shunt capacitor for balanced signal compression. The shunt capacitor and the reverse shunt capacitor may be varactors or Schottky diodes that have voltage-dependent capacitance. As a result, both rise time and fall time of the input signal are compressed along the NLTL frequency comb generator. With a sinusoidal signal input, the output signal may be close to a square wave. Such a square wave output naturally suppresses all even harmonics, which can be valuable for odd harmonics signal extraction or filtration.

A solid-state device chip including diodes (generating a higher or lower frequency output through frequency multiplication or mixing of the input frequency) and a novel on-chip diplexing design that allows combination of two or more multiplier or mixer structures operating at different frequency bands within the 50-5000 GHz range within a same chip and/or waveguide. The on-chip diplexing design consists of a single-substrate multiplier chip with two or more multiplying structures each one containing 2 or more Schottky diodes. The diodes in each structure are tuned to one portion of the target frequency band, resulting in the two or more structures working together as a whole as a large broadband multiplier or mixer. Thus, an increase in bandwidth from 10-15% (current state-of-the-art) to at least 40% is achieved. Depending on the target frequencies, each subset of diodes within the chip can be designed to work either as a doubler or a tripler.

A solid state device chip including diodes (generating a higher frequency output through frequency multiplication of the input frequency) and a novel on-chip power combining design. Together with the on-chip power combining, the chip has increased efficiency because the diodes' anodes, being micro-fabricated simultaneously on the same patch of a GaAs wafer under identical conditions, are very well balanced. The diodes' GaAs heterostructure and the overall chip geometry are designed to be optimized for high power operation. As a result of all these features, the device can generate record-setting power having a signal frequency in the F-band and W-band (30% conversion efficiency).

A frequency tripler circuit includes an amplifier to receive a balanced input signal at an input frequency and outputs a balanced signal at a second harmonic of the input frequency. The frequency tripler circuit includes a passive double balanced mixer coupled to an output of the amplifier to receive the balanced signal at the second harmonic and the balanced input signal to generate an output balanced signal having a frequency triple the input frequency.

A frequency tripler circuit includes an amplifier to receive a balanced input signal at an input frequency and outputs a balanced signal at a second harmonic of the input frequency. The frequency tripler circuit includes a passive double balanced mixer coupled to an output of the amplifier to receive the balanced signal at the second harmonic and the balanced input signal to generate an output balanced signal having a frequency triple the input frequency.

Various NLTL frequency comb generator embodiments are disclosed for compressing rise time, fall time, or both rise time and fall time of an input signal to generate an output signal comprising multiple harmonics of the input signal. The NLTL frequency comb generator may comprise a plurality of segments cascaded in series with each segment comprising a series inductor, a shunt capacitor, and a reverse shunt capacitor for balanced signal compression. The shunt capacitor and the reverse shunt capacitor may be varactors or Schottky diodes that have voltage-dependent capacitance. As a result, both rise time and fall time of the input signal are compressed along the NLTL frequency comb generator. With a sinusoidal signal input, the output signal may be close to a square wave. Such a square wave output naturally suppresses all even harmonics, which can be valuable for odd harmonics signal extraction or filtration.

Various NLTL frequency comb generator embodiments are disclosed for compressing rise time, fall time, or both rise time and fall time of an input signal to generate an output signal comprising multiple harmonics of the input signal. The NLTL frequency comb generator may comprise a plurality of segments cascaded in series with each segment comprising a series inductor, a shunt capacitor, and a reverse shunt capacitor for balanced signal compression. The shunt capacitor and the reverse shunt capacitor may be varactors or Schottky diodes that have voltage-dependent capacitance. As a result, both rise time and fall time of the input signal are compressed along the NLTL frequency comb generator. With a sinusoidal signal input, the output signal may be close to a square wave. Such a square wave output naturally suppresses all even harmonics, which can be valuable for odd harmonics signal extraction or filtration.