A voltage-controlled oscillator (VCO) includes a power supply node configured to have a power supply voltage. A reference node is configured to have a reference voltage. A transformer-coupled band-pass filter (BPF) is coupled to a pair of transistors. The pair of transistors and the transformer-coupled band-pass filter are positioned between the power supply node and the reference node.

An output buffer for an oscillator circuit and associated methodology. The output buffer has inverters and at least one negative feedback loop coupled to corresponding inverters. The negative feedback loop of the circuit is disabled in response to a control signal until one or more of a defined level of oscillation and a defined period of time is reached during start-up of the oscillator circuit, and is thereafter enabled. At least one of the inverters has at least one second negative feedback loop coupled to the corresponding inverter. An amount of feedback provided by the second negative feedback loop is adjustable in response to a control signal, where a first feedback level is present until a defined level of oscillation and/or a defined period of time is reached during start-up, a second feedback level is thereafter present in, and the first feedback level is less than the second feedback level.

A voltage controlled oscillator (VCO) and buffer circuit includes a voltage controlled oscillator (VCO), a buffer circuit configured to receive a signal generated by the VCO, the buffer circuit comprising a first transistor having a parasitic gate-source capacitance (Cgs), and a second transistor coupled across the first transistor, wherein a gate of the first transistor is coupled to a drain and a source of the second transistor, and a gate of the second transistor is coupled to a source of the first transistor.

An oscillator start-up circuit and methodology for oscillator start-up is disclosed. The circuit includes a reference bias switch coupled to a reference node and a load node of a transconductor of an oscillator. The reference bias switch is responsive to a control signal for start-up of the oscillator and operable to close at a first time prior to start-up of the oscillator to maintain a voltage at the reference node equal to a voltage at the load node prior to application of bias to the transconductor. The reference bias switch is further operable to open at a second time subsequent to the first time. In one embodiment, a separate reference bias voltage is applied to a reference node of the transconductor.

A self-biased amplifier includes a capacitor, a bias generation circuit and a common source amplifier. The capacitor is used to receive an input voltage and output an alternating component of the input voltage. The bias generation circuit is coupled to the capacitor, and used to generate a first bias voltage according to the alternating component. The common source amplifier is coupled to the bias generation circuit, and used to generate an amplified voltage according to the first bias voltage.

An oscillator includes a quartz crystal resonator and a circuit device, and the circuit device includes an oscillation circuit and a PLL circuit. The PLL circuit includes a phase comparison circuit that performs a phase comparison between the reference clock signal and a feedback clock signal, a control voltage generation circuit that generates a control voltage based on a result of the phase comparison, and a voltage control oscillation circuit that generates a clock signal having a frequency corresponding to the control voltage, and a frequency division circuit that divides a frequency of the clock signal and outputs the feedback clock signal. An oscillation frequency of the quartz crystal resonator is higher than or equal to 200 MHz, and a phase comparison frequency of the phase comparison circuit is higher than or equal to 200 MHz.

A circuit device includes first and second output signal lines from which first and second output signals constituting differential output signals are output, and first to n-th output drivers coupled to the first and second output signal lines. In a first mode, i number of output drivers of the first to n-th output drivers drive the first and second output signal lines based on first and second input signals constituting differential input signals. In a second mode, j number of output drivers of the first to n-th output drivers drive the first and second output signal lines based on the first and second input signals.

An integrated circuit device includes a first pad and a second pad electrically coupled to one end and the other end of a resonator, an oscillation circuit that is electrically coupled to the first pad and the second pad and generates an oscillation signal by causing the resonator to oscillate, and an output circuit that outputs a clock signal based on the oscillation signal. The oscillation circuit is disposed along a first side of the integrated circuit device among the first side, a second side that intersects the first side, a third side that is an opposite side of the first side, and a fourth side that is an opposite side of the second side. The first pad and the second pad are disposed in the oscillation circuit along the first side in a plan view, and the output circuit is disposed along the second side.

An injection locked frequency divider includes: a resonator circuit including first to fourth inductors; and a mixer circuit receiving an input signal with an input frequency. Each of the third and fourth inductors is coupled between a respective one of the first and second inductors and the mixer circuit. The two circuits cooperate to form a tank circuit having a free-running frequency and defining a frequency locking range which is around three times the free-running frequency and within which the input frequency falls. By at least performing mixing with a differential reference signal pair, the mixer circuit generates, based on the input signal, a differential mixed signal pair with a frequency that is one-third the input frequency.

A voltage controlled oscillator (VCO) is disclosed to provide reduced phase noise at higher operating frequencies. A buffer-first VCO configured according to an embodiment includes multiple VCO core circuits configured to provide synchronously tuned oscillator signals. Each VCO core circuit is coupled to a summing node through a buffer circuit that generates uncorrelated phase noise such that the summing node provides a summation output of the oscillator signals with reduced phase noise. A multiplexer-less VCO configured according to an embodiment includes multiple buffer-first VCO circuits configured to provide oscillator signals covering a range of frequencies. Each buffer-first VCO circuit is controlled or selected by an enable signal. Buffer circuits are configured to select one of the buffer-first VCO circuits for coupling to a transmission line during a given time period based on the enable signal. The transmission line is terminated in a matched impedance at each end of the line.