An oscillator circuit includes an oscillator transistor (Q1) having respective first, second, and control terminals, the oscillator transistor being arranged to generate a microwave oscillating signal at the first terminal. A surface integrated waveguide resonator (Y1) is connected to the second terminal of the oscillator transistor (Q1). An active bias circuit portion (202) including a negative feedback arrangement is between the first terminal of the oscillator transistor (Q1) and the control terminal of the oscillator transistor (Q1), the active bias circuit portion being arranged to supply a bias current to the control terminal of the oscillator transistor (Q1). The bias current is dependent on a voltage at the first terminal of the oscillator transistor (Q1) multiplied by a negative gain.

A biasing scheme for a frequency multiplication circuit, and transceiver using LO signals provided by the frequency multiplication circuit are described. A frequency doubler is cascaded with a mixer to provide a mm-wave oscillator signal. The combination provides a frequency triple that of the LO frequency supplied to the frequency doubler from a PLL. A small-sized replica of the frequency doubler is used to determine biasing of transconductance devices of the frequency doubler. A voltage output of the replica is amplified and the difference between the output and a reference voltage is supplied as feedback to the control terminal of the transconductance devices to bias the transconductance devices to near threshold. The biasing is replicated at the frequency doubler to compensate for PVT variations. A PTAT current source tied to the output of the replica regulates an average output current of the frequency multiplication circuit.

An oscillator circuit comprises a crystal oscillator arranged to generate an oscillation signal, a bias current generator arranged to supply a bias current to the crystal oscillator, and a feedback stage arranged to generate a feedback signal in response to an amplitude of the oscillation signal reaching an amplitude threshold. The bias current generator is arranged to: in response to a supply of power to the oscillator circuit being switched on, generate the bias current at an increasing level commencing from a first level; in response to the feedback signal, terminate the increasing; and during subsequent oscillation of the crystal oscillator, supply the bias current at a second level dependent on a final level of the bias current reached when the increasing is terminated.

An oscillator calibration circuit is presented. The oscillator calibration includes a first frequency locking circuit (FLC) coupled to a first oscillator, wherein the first FLC calibrates the frequency of the first oscillator using an over-the-air reference signal, wherein the first FLC calibrates the first oscillator prior to a data transmission session and remains free running during the data transmission session; and a second FLC coupled to a second oscillator, wherein the second FLC calibrates the frequency of the second oscillator using the over-the-air reference signal, wherein the second FLC calibrates the second oscillator immediately prior to a data transmission session and remains free running during the data transmission session.

A system includes a power receiver including an oscillator with a first coil and a second coil. The oscillator includes a first field effect transistor (FET) having first gate, first source, and first drain terminals, the first drain terminal coupled to the first coil, the first coil adapted to be inductively coupled to a third coil in a power transmitter. The oscillator also includes a first capacitor coupled to the first coil. The oscillator includes a second FET having second gate, second source, and second drain terminals, the second gate terminal coupled to the first capacitor, the second source terminal coupled to the first source terminal, and the second drain terminal coupled to the second coil, the second coil adapted to be inductively coupled to a fourth coil in the power transmitter. The oscillator includes a second capacitor coupled to the first gate terminal and coupled to the second coil.

A semiconductor integrated circuit has a first output node and a second output node that complementarily outputs an oscillation signal, a capacitance circuit, an inductor, a first inverter and a second inverter connected in parallel and in opposite directions, a bias circuit that supplies a bias voltage to the capacitance circuit, and a control circuit that controls the bias circuit and supplies a reference voltage for controlling an oscillation frequency of the oscillation signal to the capacitance circuit. The capacitance circuit includes a first variable capacitance element and a second variable capacitance element connected in series, and the control circuit controls the bias voltage based on a change in an oscillation frequency of the oscillation signal when a voltage level of the reference voltage supplied to a connection node of the first variable capacitance element and the second variable capacitance element is changed in a plurality of ways.

An antenna apparatus comprises: a first substrate including an antenna array in which a plurality of active antennas each including an antenna and a semiconductor structure configured to generate or detect an electromagnetic wave are provided, and a wiring electrically connected to the plurality of active antennas; and a second substrate stacked on the first substrate and including a control circuit of the antenna array, wherein the first substrate and the second substrate are bonded at a bonding surface, the control circuit is electrically connected to the antenna array via the wiring, and the control circuit of the second substrate controls oscillations of the plurality of active antennas of the first substrate.

An oscillator circuit includes an oscillator transistor (Q1) having respective first, second, and control terminals, the oscillator transistor being arranged to generate a microwave oscillating signal at the first terminal. A surface integrated waveguide resonator (Y1) is connected to the second terminal of the oscillator transistor (Q1). An active bias circuit portion (202) including a negative feedback arrangement is between the first terminal of the oscillator transistor (Q1) and the control terminal of the oscillator transistor (Q1), the active bias circuit portion being arranged to supply a bias current to the control terminal of the oscillator transistor (Q1). The bias current is dependent on a voltage at the first terminal of the oscillator transistor (Q1) multiplied by a negative gain.

An oscillator circuit includes a total of N (N≥2) class-D oscillator circuits stacked together between a supply voltage node and a reference voltage node. The output ports of adjacent class-D oscillator circuits in the disclosed oscillator circuit are coupled together by capacitors to ensure frequency and phase synchronization for the frequency signals generated by the class-D oscillator circuits. Compared with a reference oscillator circuit formed of a single class-D oscillator circuit, the oscillation amplitude of each of the class-D oscillator circuits in the disclosed oscillator circuit is 1/N of that of the reference oscillator circuit, and the current consumption of the disclosed oscillator circuit is 1/N of that of the reference oscillator circuit.

An oscillator circuit includes a total of N (N≥2) class-D oscillator circuits stacked together between a supply voltage node and a reference voltage node. The output ports of adjacent class-D oscillator circuits in the disclosed oscillator circuit are coupled together by capacitors to ensure frequency and phase synchronization for the frequency signals generated by the class-D oscillator circuits. Compared with a reference oscillator circuit formed of a single class-D oscillator circuit, the oscillation amplitude of each of the class-D oscillator circuits in the disclosed oscillator circuit is 1/N of that of the reference oscillator circuit, and the current consumption of the disclosed oscillator circuit is 1/N of that of the reference oscillator circuit.