A voltage setting circuit includes a frequency comparator that compares the oscillation frequencies of a first distributed voltage-controlled oscillator and a second distributed voltage-controlled oscillator and a frequency determination circuit that determines the levels of the oscillation frequencies of the first distributed voltage-controlled oscillator and the second distributed voltage-controlled oscillator. The bias to be supplied to the first distributed voltage-controlled oscillator and the bias to be supplied to the second distributed voltage-controlled oscillator are determined in accordance with a result of the determination. The bias at a time when the levels of the oscillation frequencies are reversed is determined to be the optimum bias, and the optimum bias is supplied to the core circuit.

An oscillator circuit includes a total of N (N2) class-D oscillator circuits stacked together between a supply voltage node and a reference voltage node. The output ports of adjacent class-D oscillator circuits in the disclosed oscillator circuit are coupled together by capacitors to ensure frequency and phase synchronization for the frequency signals generated by the class-D oscillator circuits. Compared with a reference oscillator circuit formed of a single class-D oscillator circuit, the oscillation amplitude of each of the class-D oscillator circuits in the disclosed oscillator circuit is 1/N of that of the reference oscillator circuit, and the current consumption of the disclosed oscillator circuit is 1/N of that of the reference oscillator circuit.

Oscillator calibration circuits and wireless transmitters including oscillator calibration circuits. An oscillator calibration circuit includes a first frequency locking circuit (FLC) coupled to a first oscillator, wherein the first FLC calibrates the frequency of the first oscillator using an over-the-air reference signal, wherein the first FLC calibrates the first oscillator prior to a data transmission session and remains free running during the data transmission session.

A Pierce oscillator is provided with a transconductance amplifier transistor having a DC drain voltage that is regulated to equal a reference voltage independently from a DC gate voltage for the transconductance amplifier transistor.

Apparatuses and methods for quadrature signal generation are provided. An example includes a quadrature signal generator. The quadrature signal generator is configured to generate, based on a received differential signal, a plurality of quadrature clock signals at a same frequency as that of the received differential signal. The quadrature signal generator is also configured to provide the plurality of quadrature clock signals to a memory system.

A phase-locked loop comprises a voltage controlled oscillator. The voltage controlled oscillator comprises an inductor and a capacitor, connected in parallel, and also connected in parallel therewith, a negative resistance structure. A first terminal of the negative resistance structure is connected to respective first terminals of the inductor and the capacitor. A second terminal of the negative resistance structure is connected to respective second terminals of the inductor and the capacitor. The negative resistance structure exhibits a tunable capacitance, such that a frequency of an output of the voltage controlled oscillator can be tuned by a control input signal, and the control input signal is generated in the phase-locked loop. The negative resistance structure comprises first and second transistors. There is a first conduction path between the first terminal of the first transistor and the control terminal of the second transistor, and a second conduction path between the control terminal of the first transistor and the first terminal of the second transistor. The control terminal of at least one of the first and second transistors is biased by the control input signal, such that a parasitic capacitance of said at least one of the first and second transistors can be tuned by the control input signal, in order to tune the frequency of the output of the voltage controlled oscillator, and hence the frequency of oscillation of the phase-locked loop.

A crystal driver integrated circuit configurable for daisy chaining including an amplifier core, an input pin and an output pin, and a controller that operates the amplifier core in any one of multiple operating modes. The operating modes include an oscillator mode for driving an external crystal coupled between the input and output pins to generate an oscillation signal at a target frequency, and an amplifier mode that amplifies an external oscillating signal provided to the input pin to provide an amplified oscillation signal on the output pin. The amplifier core includes a controllable current source that provides a core bias current to an amplifier having a level that is adjusted depending upon the operating mode and desired amplitude. The operating modes may include a bypass mode in which the amplifier core is disabled. The amplifier may be implemented as either an PMOS amplifier or an NMOS amplifier.

In an example, a voltage-controlled oscillator (VCO) includes: an oscillator having a supply input; and a voltage regulator, coupled to the supply input. The voltage regulator includes: a first transistor and a second transistor providing a first source-coupled transistor pair, and a third transistor and a fourth transistor providing a second source-coupled transistor pair; an active load coupled to drains of the first, second, third, and fourth transistors; a first current source coupled to sources of the first and second transistors, and a second current source coupled to sources of the third and fourth transistors; a fifth transistor having a source and a drain coupled to the source and the drain, respectively, of the first transistor; and a sixth transistor having a source and a drain coupled to the source and the drain, respectively, of the third transistor.

The present disclosure describes aspects of a switchable inductor network for wideband circuits. In some aspects, the switchable inductor network provides selectable inductance. The switchable inductor network includes a first coil and a second coil that includes a first inductive segment and a second inductive segment. Connection points of the second coil connect the second coil across a portion of the first coil. The switchable inductor network also includes a switch connected between the first inductive segment and the second inductive segment of the second coil. The switch is configured to change the selectable inductance of the switchable inductor network by selectively coupling the first inductive segment to the second inductive segment of the second coil in response to a control signal.

Across the entire operating temperature range, and without requiring a new transistor element, the constant voltage output by a constant voltage circuit can be controlled to a voltage greater than or equal to the stop-oscillating voltage and as low as possible. A resistance 11b that negatively feeds back a reference current Iref is connected between the gate and source of a depletion mode n-channel transistor 11a configured to produce the reference current Iref on which the constant voltage VREG is based. The resistance of resistance 11b has a gradient to temperature change of the same sign as the gradient of the difference between the constant voltage and the stop-oscillating voltage to temperature change when the gradient of the resistance value of the resistance to temperature change is 0.