A low voltage crystal oscillator (XTAL) driver with feedback controlled duty cycling for ultra low power biases an amplifier for an XTAL in the sub-threshold operating regime. A feedback control scheme can be used to bias the amplifier for an XTAL biased in the sub-threshold operating regime. The amplifier of a XTAL oscillator can be duty cycled to save power, e.g., the XTAL driver can be turned off to save power when the amplitude of the XTAL oscillation reaches a maximum value in range; but be turned back on when the amplitude of the XTAL oscillation starts to decay, to maintain the oscillation before it stops. In addition or alternatively, a feedback control scheme to duty cycle the amplifier of a XTAL oscillator can be used to monitor the amplitude of the oscillation.

The present disclosure describes a low-power, low-phase-noise (LPLPN) oscillator. The LPLPN oscillator includes a resonator load, an amplifier stage, and a loop gain control circuit. The resonator load is structured to resonate at a primary resonant frequency. The amplifier stage is coupled with the resonator load to develop a loop gain that peaks at the primary resonant frequency. The loop gain control circuit is coupled with the amplifier stage, and it is structured to regulate the loop gain for facilitating the amplifier stage to generate an oscillation signal at the primary resonant frequency and suppress a noise signal at a parasitic parallel resonant frequency (PPRF).

The oscillation circuit 1 comprises: an oscillator X1; a first capacitance CF having one end connected to the oscillator X1; a second capacitance CO having one end connected to the other end of the first capacitance CF; an output terminal Vo connected to a connection point N2 of the first capacitance CF and the second capacitance CO; an amplifier circuit A1 connected between a node between the oscillator X1 and the first capacitance CF and a connection point N2 of the first capacitance CF and the second capacitance CO to form an oscillation loop together with the first capacitance CF; a differential amplifier circuit A2 arranged on the oscillation loop; and a feedback path 3 configured to feed a part of an output on the output terminal Vo to the differential amplifier circuit A2.

A low power mode control module for a crystal oscillator which performs the following steps: detecting whether an oscillation output signal of the crystal oscillator is output stably; when the oscillation output signal of the crystal oscillator is output stably, comparing at least one of an oscillation input signal and the oscillation output signal with an amplitude control signal to determine whether to adjust the amplitude control signal; when the amplitude control signal does not need to be adjusted, generating an upper bound reference voltage and a lower bound reference voltage associated with the amplitude control signal; and according to whether the oscillation output signal exceeds a reference voltage range of the upper reference voltage and the lower reference voltage, generating a low power mode control output signal associated with a crystal oscillator enable signal for enabling the crystal oscillator.

A circuit device is configured to switching between a first mode in which phase noise of an output clock signal is low and a second mode in which power consumption is small, and includes an oscillation circuit configured to generate an oscillation signal, an output circuit configured to output the output clock signal, a temperature sensor configured to output a temperature detection signal, a temperature compensation circuit configured to perform temperature compensation on an oscillation frequency based on the temperature detection signal, and a control circuit. The control circuit performs control such that a power supply voltage supplied to the oscillation circuit in the first mode is higher than a power supply voltage supplied to the oscillation circuit in the second mode. In addition, the control circuit performs control such that at least one of a reference voltage supplied to the temperature compensation circuit and a reference current supplied to the temperature sensor does not change between the first mode and the second mode.

A crystal oscillator includes a current source that charges a capacitor. A charge on the capacitor is periodically injected into a crystal of the crystal oscillator. A switch couples the capacitor to the crystal and a timing circuit controls the switch to cause the charge to be injected beginning at approximately a peak of a crystal output signal. The timing circuit is configurable into a self-resonant mode for calibration of a delay through the timing circuit by coupling an output of the timing circuit to an input of the timing circuit. A comparator compares a magnitude of the crystal output signal to a reference voltage and supplies compare results to a gain control circuit. The gain control circuit adjusts the current from the current source to adjust the charge being injected into the crystal from the capacitor to thereby control the magnitude of the crystal output signal.

A device includes an oscillator including at least one inductor and at least one capacitor and configured to generate, based on a positive supply voltage, an output signal oscillating in a resonance frequency of the at least one inductor and the at least one capacitor. The device further includes an oscillation detector configured to determine whether the output signal oscillates based on a clock signal and increase a loop gain of the oscillator until the output signal oscillates.

A clock integrated circuit is provided. The clock integrated circuit includes: a first clock generator which includes a crystal oscillator configured to generate a first clock signal; and a second clock generator which includes a resistance-capacitance (RC) oscillator and a first frequency divider, and is configured to: generate a second clock signal using the first frequency divider based on a clock signal output from the RC oscillator; perform a first calibration operation for adjusting a frequency division ratio of the first frequency divider to a first frequency division ratio based on the first clock signal; and perform a second calibration operation for adjusting the first frequency division ratio to a second frequency division ratio based on a sensed temperature.

A circuit device is configured to switching between a first mode in which phase noise of an output clock signal is lower than that in a second mode and the second mode in which power consumption is smaller than that in the first mode, and the circuit device includes an oscillation circuit configured to generate an oscillation signal, a waveform shaping circuit configured to perform waveform shaping on the oscillation signal to obtain a rectangular wave clock signal; and an output circuit configured to output the output clock signal based on the clock signal. A driving capability of the waveform shaping circuit in the first mode is higher than a driving capability of the waveform shaping circuit in the second mode.

An oscillator circuit portion 200 including a resonator 216 arranged to oscillate with a resonant frequency, a capacitor 208 arranged to provide charge to the resonator, a first switch 206 arranged to connect the capacitor to an input voltage to charge the capacitor, a second switch 210 arranged to connect the resonator to the capacitor, and a timing circuit 202 configured to generate periodically a first pulse PULSE_L and a second pulse PULSE_H. The first pulse is configured to close the first switch, the second pulse is configured to close the second switch, and the first and second switches are arranged to be open when the timing circuit is not generating the first or second pulses, to maintain oscillation of the resonator.