An device having an oscillator circuit modifiable between a first operating mode and a second operating mode, wherein the first operating mode has a first frequency accuracy and a first power consumption, wherein the second operating mode has a second frequency accuracy and a second power consumption, wherein the second frequency accuracy is more accurate than the first frequency accuracy and the second power consumption is higher than the first power consumption, and a control circuit in communication with the oscillator circuit to modify the operating mode of the oscillator circuit.

A low power crystal oscillator circuit having a high power part and a low power part. Oscillation is initialized using the high power part. Once the crystal is under stable oscillation, the circuit switches to the low power part and continue operation for a long duration.

A Pierce oscillator is provided with a transconductance amplifier transistor having a DC drain voltage that is regulated to equal a reference voltage independently from a DC gate voltage for the transconductance amplifier transistor.

A relaxation oscillator can provide a smaller and cheaper alternative to a crystal oscillator circuit in a wide variety of applications. A sawtooth relaxation oscillator can include overshoot error integration. Separate and distinct oscillator capacitor charging, overshoot error integration, and reset phases can be provided using separate comparators for first and second oscillation capacitors. Potential advantages can include high accuracy high-frequency clock, convenient trimming during initial calibration, clock frequency stability over temperature and time, fast startup with low overshoot, high power supply rejection, low power, or low noise/jitter. The oscillator can charge an oscillation capacitor up to a target voltage, then interrupt charging before beginning an error integration phase that adjusts the target voltage by integrating an overshoot error of a voltage on the oscillation capacitor. After completing the overshoot error integration, the voltage on the oscillation capacitor can be reset. The techniques described are believed to be capable of improving clock frequency accuracy and other characteristics.

In an example, a voltage-controlled oscillator (VCO) includes: an oscillator having a supply input; and a voltage regulator, coupled to the supply input. The voltage regulator includes: a first transistor and a second transistor providing a first source-coupled transistor pair, and a third transistor and a fourth transistor providing a second source-coupled transistor pair; an active load coupled to drains of the first, second, third, and fourth transistors; a first current source coupled to sources of the first and second transistors, and a second current source coupled to sources of the third and fourth transistors; a fifth transistor having a source and a drain coupled to the source and the drain, respectively, of the first transistor; and a sixth transistor having a source and a drain coupled to the source and the drain, respectively, of the third transistor.

A wireless communication device is presented for use with a sensor. The wireless communication device includes: an antenna, a driver circuit and a bias circuit. The driver circuit is electrically coupled to the antenna and includes at least one pair of cross-coupled transistors. The bias circuit is electrically coupled to the driver circuit. In a transmit mode, the bias circuit biases the driver circuit with a first bias current. In response to the first bias current, the driver circuit oscillates the antenna. In a receive mode, the bias circuit biases the driver circuit with a second bias current, such that the first bias current differs from the second bias current. In response to the second bias current, the bias circuit amplifies a signal received by the antenna.

A semiconductor device including: a resistor element connected to one and another end of a crystal oscillator; an adjustable current type inverter element having an input connected to one end of the resistor element and an output connected to another end of the resistor element; a first capacitor element connected to the input of the inverter element and to ground; a second capacitor element having one end connected to ground; a first switching element that switches a connection state of the one end of the first capacitor element and another end of the second capacitor element; a third capacitor element connected to the output of the inverter element and to ground; a fourth capacitor element having one end connected to ground; and a second switching element that switches a connection state of the one end of the third capacitor element and another end of the fourth capacitor element.

Across the entire operating temperature range, and without requiring a new transistor element, the constant voltage output by a constant voltage circuit can be controlled to a voltage greater than or equal to the stop-oscillating voltage and as low as possible. A resistance 11b that negatively feeds back a reference current Iref is connected between the gate and source of a depletion mode n-channel transistor 11a configured to produce the reference current Iref on which the constant voltage VREG is based. The resistance of resistance 11b has a gradient to temperature change of the same sign as the gradient of the difference between the constant voltage and the stop-oscillating voltage to temperature change when the gradient of the resistance value of the resistance to temperature change is 0.

An oscillator for generating oscillation signals at two output terminals includes an inductor coupled between the two output terminals, a capacitor coupled between the two output terminals, two P-type transistors and two N-type transistors. Source electrodes of the two P-type transistors are coupled to a supply voltage, and gate electrodes of the two P-type transistors are coupled to the two output terminals, respectively. Source electrodes of the two N-type transistors are coupled to a supply voltage, gate electrodes of the two N-type transistors are coupled to the two output terminals, respectively, and drain electrodes of the two N-type transistors are coupled to drain electrodes of the two P-type transistors, respectively. In addition, the drain electrodes of the two N-type transistors are coupled to two internal nodes of the inductor.

A crystal oscillator circuit is provided. The crystal oscillator circuit includes an oscillator start-up circuit having a first output terminal and a second output terminal, where the second output terminal outputs a first oscillation signal; and a waveform conversion circuit configured to convert the first oscillation signal to a rectangular wave signal. The crystal oscillator circuit also includes a first current source configured to output a first current to drive the oscillator start-up circuit; and a second current source configured to output a second current, and being connected in parallel with the first current source to jointly drive the oscillator start-up circuit. Further the crystal oscillator circuit includes a pulse generation circuit configured to generate a control pulse signal to control the second current source to output the second current after power on and to stop outputting the second current after a preset time.