A crystal oscillator is provided. The crystal oscillator includes a crystal resonator including a pair of terminals and being capable of oscillating at a fundamental resonance frequency and at least one overtone resonance frequency. Further, the crystal oscillator includes an inverter circuit coupled between the pair of terminals. The crystal oscillator additionally includes a suppression circuit configured to suppress oscillation of the crystal resonator at the fundamental resonance frequency. Further, the crystal oscillator includes a control circuit configured to control a switch circuit for selectively coupling the suppression circuit to the crystal resonator.

An oscillator includes: a resonator; an oscillation circuit configured to generate an oscillation signal by the resonator; a clock output terminal; an output circuit configured to output a clock signal to an external processing device via the clock output terminal; a first terminal; and an interface circuit configured to execute communication with the processing device by a data signal. In the communication, the output circuit outputs the clock signal to the processing device that is a master for the communication, and the interface circuit that is a slave for the communication receives, via the first terminal, the data signal that is transmitted from the processing device and synchronized with the clock signal, or transmits, via the first terminal, the data signal to the processing apparatus in synchronization with the clock signal.

An oscillation module includes: an oscillation circuit; a multiplication circuit which is provided at a stage subsequent to the oscillation circuit and is operated by differential motion; and an output circuit which is provided at a stage subsequent to the multiplication circuit.

An apparatus is provided which comprises: a crystal having an input and an output; a first interconnect line having first and second ends, wherein the first end is coupled to the input; a second interconnect line having first and second ends, wherein the first end is coupled to the output; a first capacitor coupled to the input and ground; and a second capacitor coupled to the second end of the second interconnect line. An apparatus is provided which comprises: a high pass filter; a pair of AC coupling capacitors coupled to the high pass filter; a low pass filter coupled to the pair of AC coupling capacitors; and an analog to digital converter (ADC) coupled to the low pass filter.

A voltage setting circuit includes a frequency comparator that compares the oscillation frequencies of a first distributed voltage-controlled oscillator and a second distributed voltage-controlled oscillator and a frequency determination circuit that determines the levels of the oscillation frequencies of the first distributed voltage-controlled oscillator and the second distributed voltage-controlled oscillator. The bias to be supplied to the first distributed voltage-controlled oscillator and the bias to be supplied to the second distributed voltage-controlled oscillator are determined in accordance with a result of the determination. The bias at a time when the levels of the oscillation frequencies are reversed is determined to be the optimum bias, and the optimum bias is supplied to the core circuit.

A circuit device includes an A/D conversion unit, a processing unit that performs a temperature compensation process of an oscillation frequency based on temperature detection data and outputs frequency control data of the oscillation frequency, a D/A conversion unit, and an oscillation circuit. The D/A conversion unit (area DAC) is disposed on a first direction DR1 side of the A/D conversion unit (area ADC). When a direction crossing the first direction DR1 is defined as a second direction DR2, the processing unit (area DSPL) is disposed on the second direction DR2 side of the A/D conversion unit and the D/A conversion unit. When a direction opposite to the second direction DR2 is defined as a third direction DR3, the oscillation circuit (area OSC) is disposed on the third direction DR3 side or the first direction DR1 side of the D/A conversion unit.

A quadrature oscillator includes a first oscillator that outputs a first differential signal, and a second oscillator that outputs a second differential signal having phases that are different from those of the first differential signal, wherein the first oscillator includes a first LC resonator having an inductor and a capacitor coupled in parallel, a first cross-coupled circuit having a first pair of cross-coupled transistors coupled to the first LC resonator, a first tail current source coupled to the first pair of transistors, first input differential pair transistors to which the second differential signal is to be input, and a first pair of harmonic resonators disposed in input sections of the first input differential pair transistors, the first pair of the harmonic resonators have a resonance frequency of an odd multiple of a resonance frequency of the first oscillator.

An oscillator circuit topology using a one-pin external resonator suitable for integrated-circuit low-voltage, low-power applications that require a fast-starting accurate clock is disclosed. The circuit incorporates a novel arrangement of a plurality of active transconductance cells that respond to a digital control and provide adjustable loop gain for the oscillator. A programmable number of start-up transconductance cells are engaged in the initial phase of the oscillation for temporarily increasing the loop gain and energizing the resonator, and are disengaged from the oscillator core once the oscillation level is sufficiently large. The start-up transconductance cells may be identical to the always-on transconductance cells in the oscillator core, or they may be scaled versions of those cells. In addition, a programmable number of identical or scaled transconductance cells may be provided in the oscillator core itself, for accommodating different resonators. Internal circuit implementations of the transconductance cells that enable their efficient combination for increasing the oscillator loop gain are also disclosed.

An apparatus is provided which comprises: an oscillator circuit to generate a clock signal and transmit the clock signal over a signal line; a ground reference plane associated with the signal line; and one or more patterns formed in the ground reference plane, wherein the one or more patterns in the ground reference plane is to filter out noise from the clock signal transmitted over the signal line.

Techniques pertaining to designs of integrated circuits having on-chip inductors with low common mode coupling effect are described. According to one aspect of the present invention, an integrated circuit is designed to have a first circuit operating at a first frequency and including a first inductor, and a second circuit including a second inductor and provided to process an input signal. The second circuit includes a second inductor and is provided to process an input signal. The second inductor includes a first terminal, a second terminal, an intermediate terminal, and an intermediate node, wherein a first wire is formed between the first terminal and the intermediate node, a second wire is formed between the intermediate node and the second terminal, and an intermediate tap is coupled between the intermediate node and the intermediate terminal, the first wire and the second wire forming a coil with one or more turns, and the first terminal, the second terminal and the intermediate terminal of the second inductor being located on one side of the coil and adjacent to each other.