A variable reactance apparatus, tunable oscillator and method for changing a gain associated with an input signal of a tunable oscillator are disclosed. An embodiment of the variable reactance apparatus comprises includes a plurality of unit variable reactance structures comprising including respective control input nodes, and a control circuit configured to connect each of the control input nodes to a respective signal from among a plurality of signals comprising including a first tuning signal and a second tuning signal. An embodiment of a tunable oscillator comprises includes a resonance circuit, a negative impedance structure and a variable reactance apparatus configured for tuning of the oscillator. An embodiment of a method comprises includes altering connections of first and second tuning signals to control input nodes of respective first and second sets of unit variable reactance structures while holding constant a sum of the number of unit variable reactance structures in the first and second sets.

A key based technique that targets obfuscation of critical circuit parameters of an analog circuit block by masking physical characteristics of a transistor (width and length) and the circuit parameters reliant upon these physical characteristics (i.e. circuit biasing conditions, phase noise profile, bandwidth, gain, noise figure, operating frequency, etc.). The proposed key based obfuscation technique targets the physical dimensions of the transistors used to set the optimal biasing conditions. The widths and/or lengths of a transistor are obfuscated and, based on an applied key sequence, provides a range of potential biasing points. Only when the correct key sequence is applied and certain transistor(s) are active, are the correct biasing conditions at the target node set.

Provided is a voltage-controlled oscillator capable of suppressing performance deterioration due to a leak current of a variable capacitive element. Each of the first capacitive circuit and the second capacitive circuit includes a variable capacitive element, a capacitive element, a detection circuit, and a compensation circuit. The variable capacitive element is provided between nodes. A capacitance value of variable capacitive element depends on a voltage value between the nodes. The detection circuit applies a bias voltage value to the second node, and detects an amount of leak current flowing through the variable capacitive element. The compensation circuit causes a current for compensating for the leak current of the variable capacitive element to flow through the first node on the basis of a detection result of the detection circuit.

A resonant tank includes a first capacitor formed on a semiconductor substrate, a first inductor formed on the semiconductor substrate, a second capacitor formed on the semiconductor substrate, and a second inductor formed on the semiconductor substrate. The first capacitor, the first inductor, the second capacitor, and the second inductor are connected in a ring configuration, with each capacitor connected between a pair of the inductors and with each inductor connected between a pair of the capacitors. An amplifier circuit is coupled to the resonant tank and configured to amplify a signal in the resonant tank.

A circuit device includes an oscillation circuit and a processing circuit. The oscillation circuit includes a variable capacitance circuit configured by a capacitor array and oscillates at an oscillation frequency corresponding to the capacitance value of the variable capacitance circuit. First temperature data and second temperature data subsequent to the first temperature data are input to the processing circuit as temperature data. In the period between the start of the capacitance control based on the first temperature data and the start of the capacitance control based on the second temperature data, the processing circuit switches the first capacitance control data corresponding to the first temperature data and the second capacitance control data different from the first capacitance control data in a time-division manner to be output to the variable capacitance circuit.

Rotary traveling wave oscillators (RTWOs) with distributed stubs are provided. In certain embodiments, an RTWO includes segments that are implemented using distributed stubs to mitigate flicker noise upconversion arising from transmission line dispersion. For example, a distance between the distributed stubs can be selected to intentionally generate a phase difference between transmission line modes, thereby cancelling out phase shifts due to transmission line dispersion. In particular, each segment is subdivided into multiple transmission line sections with a maintaining amplifier electrically connected to one of the sections and a tuning capacitor array connected to adjacent transmission line sections.

This document presents an oscillator circuit and method. The oscillator circuit has a crystal to generate an oscillating voltage signal, a load capacitor coupled to the crystal, a capacitive element, and a switching circuit. The switching circuit alternately connects the capacitive element to the load capacitor and disconnects the capacitive element from the load capacitor. The presented oscillator circuit shows the advantages of a lower power consumption and a smaller circuit area.

A phased-locked loop (PLL) circuit with an injection locked digital digitally controlled oscillator (ILD) that has an ILD control input element, an ILD injection input element and an ILD output element. The PLL circuit also includes an adaptive control unit (ACU), wherein the ACU is configured to receive an error signal and is configured to output an ILD control word. The ILD control input element is configured to receive the ILD control word, and the ILD control word may set a natural oscillation frequency of the ILD. The ILD is further configured to output a first output signal from the ILD output element, where the natural oscillation frequency may set a frequency of the first output signal.

A method and circuit for linearizing a frequency response of an oscillator controlled by a plurality of capacitor banks are disclosed. In the disclosed method, for each capacitor bank of at least two capacitor banks of the oscillator, a respective sensitivity characteristic of the capacitor bank is determined. Further, a set of reference output frequency control words (FCWs) for an associated set of frequencies of the oscillator are determined. When an input FCW is received and an output FCW is responsively provided based on (i) an interpolation between two reference output FCWs of the set of reference output FCWs and (ii) the respective sensitivity characteristics of the at least two capacitor banks of the oscillator. The output FCW is then applied to the at least two capacitor banks of the oscillator.

The disclosure is directed to a frequency synthesizer circuit including digitally controlled oscillator (DCO) and an injection locked digitally controlled oscillator (ILD). The ILD outputs a signal with a frequency that is some fraction of the frequency of the DCO output signal and locked in phase to the DCO output signal. The frequency synthesizer circuit drives the ILD with the same modulation input signal that drives the DCO, with the modulation input signal scaled to account for any mismatch between the gains of the DCO and ILD. Driving the ILD with the same, scaled modulation signal as the main DCO minimizes the frequency offset between the DCO output signal and the divided natural oscillation frequency of the ILD. Minimizing the frequency offset makes the lock of the ILD more robust and reduces jitter contribution from the ILD.