A method for enhancing linearity of the receiver front-end system includes receiving a radio frequency signal by an antenna, converting the radio frequency signal to first differential signals by a transformer module, adjusting frequencies of the first differential signals to generate second differential signals by a mixer module, detecting a common signal in order to reduce a common error of the second differential signals, and generating third differential signals according to a reference signal after the common error is reduced from the second differential signals. The first differential signals, the second differential signals, and the third differential signals are unbalanced.

Methods and devices providing Positive Logic biasing schemes for use in a digitally tuning capacitor in an integrated circuit device are described. The described methods can be used in integrated circuits with stringent requirements in terms of switching time, power handling, noise sensitivity and power consumption. The described devices include DC blocking capacitors arranged in series with stacked switches coupled to RF nodes. The stacked FET switches receive non-negative supply voltages through their drains and gates during the ON and OFF states to adjust the capacitance between the two nodes.

A phase-locked loop comprises a voltage controlled oscillator. The voltage controlled oscillator comprises an inductor and a capacitor, connected in parallel, and also connected in parallel therewith, a negative resistance structure. A first terminal of the negative resistance structure is connected to respective first terminals of the inductor and the capacitor. A second terminal of the negative resistance structure is connected to respective second terminals of the inductor and the capacitor. The negative resistance structure exhibits a tunable capacitance, such that a frequency of an output of the voltage controlled oscillator can be tuned by a control input signal, and the control input signal is generated in the phase-locked loop. The negative resistance structure comprises first and second transistors. There is a first conduction path between the first terminal of the first transistor and the control terminal of the second transistor, and a second conduction path between the control terminal of the first transistor and the first terminal of the second transistor. The control terminal of at least one of the first and second transistors is biased by the control input signal, such that a parasitic capacitance of said at least one of the first and second transistors can be tuned by the control input signal, in order to tune the frequency of the output of the voltage controlled oscillator, and hence the frequency of oscillation of the phase-locked loop.

Certain aspects of the disclosure are directed to electrostatic discharge protection of an integrated circuit clock. According to a specific example, circuitry includes a direct-current power supply, a voltage-controlled oscillation (VCO) circuit, an electrostatic protection circuit, and a voltage regulator. The VCO circuit has an oscillation frequency and includes an amplification circuit and capacitance circuitry. The electrostatic protection circuit is arranged to connect power to the VCO circuit while reducing variation in the oscillation frequency of the VCO circuit resulting from electrostatic energy. The voltage regulator is connected between the direct-current power supply and a power supply connection at which the direct-current power is connected to the VCO, and is configured to mitigate an imbalance of electric charges from adversely altering a tuning capacitance of the VCO established by the capacitance circuitry.

In some embodiments, the present disclosure relates to a frequency generator having a resistor network and a capacitor network. The capacitor network has a plurality of capacitors connected in parallel with one another. A comparator is configured to output an oscillating voltage signal. An input of the comparator is connected to the output of the resistor network and the output of the capacitor network. A frequency testing circuit is configured to calculate a frequency of the oscillating voltage signal and determine whether the frequency is within a range of an expected frequency. The frequency testing circuit may also be configured to selectively connect a first plate of the plurality of capacitors to a non-varying voltage or to the input of the capacitor network to adjust a frequency of the oscillating voltage signal.

A frequency-modulated continuous-wave radar system includes a waveform generator, a delta-sigma modulation circuit, a voltage controlled oscillator, a frequency divider circuit, a control circuit, an injection locked oscillator, a power amplifier circuit, a first power detection circuit, a second power detection circuit, a third power detection circuit, and a calibration engine circuit. The waveform generator, the delta-sigma modulation circuit, the voltage controlled oscillator, the frequency divider circuit, and the control circuit form a phase locked loop. The calibration engine circuit is coupled to the delta-sigma modulation circuit, the voltage controlled oscillator, the injection locked oscillator, the power amplifier circuit, the first power detection circuit, the second power detection circuit, and the third power detection circuit for adjusting frequency gains of the voltage controlled oscillator, the injection locked oscillator, and the power amplifier circuit to approach wideband flatness frequency responses.

An oscillating circuit has an injection-locked oscillator (ILO) and a calibration circuit. The ILO has a Gm cell and an LC tank. A first node of the Gm cell receives a first injection signal, and a second node of the Gm cell receives a second injection signal. The first injection signal and the second injection signal are differential signals. The Gm cell provides a negative resistance between a first output end and a second output end of the Gm cell. When the calibration circuit tunes a resonant frequency of the LC tank of the ILO, the magnitude of the negative resistance is reduced to control the ILO to stop self-oscillating. After finishing tuning the resonant frequency of the LC tank, the calibration circuit controls the ILO to start self-oscillating by increasing the magnitude of the negative resistance.

A method for enhancing linearity of the receiver front-end system includes receiving a radio frequency signal by an antenna, converting the radio frequency signal to first differential signals by a transformer module, adjusting frequencies of the first differential signals to generate second differential signals by a mixer module, detecting a common signal in order to reduce a common error of the second differential signals, and generating third differential signals according to a reference signal after the common error is reduced from the second differential signals. The first differential signals, the second differential signals, and the third differential signals are unbalanced.

A low voltage inverter-based amplifier includes a first inverter-based amplification module, a second inverter-based amplification module, an inverter-based feedforward module, and an inverter-based common mode detector. The first inverter-based amplification module receives an input signal. The second inverter-based amplification module receives the input signal through the inverter-based feedforward module, and receives a first output signal from the first inverter-based amplification module. The inverter-based common mode detector receives an amplified signal from the second inverter-based amplification module, and outputs a feedback signal to the second inverter-based amplification module. Since the first and the second inverter-based amplification modules are both inverter-based, the supply voltage of the low voltage inverter-based amplifier is provided to supply one PMOS and one NMOS for normal operation. Therefore, a number of cascade MOSs of the low voltage inverter-based amplifier is two, and the low voltage inverter-based amplifier can be normally operated under the low supply voltage.

A divider-less phase locked loop (PLL) includes a phase frequency detector (PFD), a charge pump (CP), a voltage controlled oscillator (VCO), a delay unit, and a clock gating unit. The PFD is electrically connected to the VCO through the CP, and the CP outputs a voltage control signal to the VCO. The VCO generates an output signal. The delay unit receives and delays a reference signal to generate a delay signal. The clock gating unit samples the output signal according to the delay signal. Since the clock gating unit samples the output signal according to the delay signal, the divider-less PLL does not need to include a divider to divide a frequency of the output signal. Therefore, power consumption of the divider-less PLL can be reduced.