H03D1/04

Sub-sampling receiver

Provided is a wireless signal receiver including: an analog-digital converter (ADC) converting an analog RF signal into a digital baseband signal; and a sub-sampling block dividing and processing the digital baseband signal into a first path signal and a second path signal, and extracting a complex baseband signal by using a relative sample delay difference between the first and second path signals, wherein the first path signal is a signal obtained by adjusting a sample delay and sampling rate of the digital baseband signal, and the second path signal is a signal obtained by filtering without adjusting the sampling rate of the digital baseband signal.

Apparatus and method for sending and receiving broadcast signals

Disclosed herein is a broadcast signal receiver. A broadcast signal receiver according to an embodiment of the present invention includes a synchronization and demodulation unit configured to perform signal detection and OFDM demodulation on a received signal, a frame parser configured to parse the signal frame of the received signal, a time deinterleaving unit configured to deinterleave LDM data, a first demapping/decoding unit configured to obtain the data of a core layer by demapping and FEC-decoding the LDM data, an interference removal unit configured to remove the core layer data from the LDM data and to output the data of an enhanced layer, and a second demapping/decoding unit configured to demap and FEC-decode the enhanced layer data.

Apparatus for transmitting broadcast signals, apparatus for receiving broadcast signals, method for transmitting broadcast signals and method for receiving broadcast signals

A method and an apparatus for receiving broadcast signals thereof are disclosed. The apparatus for receiving broadcast signals, the apparatus comprises a receiver to receive the broadcast signals, a demodulator to demodulate the received broadcast signals by an OFDM (Orthogonal Frequency Division Multiplex) scheme, a frame parser to parse a signal frame from the demodulated broadcast signals, wherein the signal frame includes service data corresponding to each of a plurality of physical paths, a time deinterleaver to time deinterleave service data in each physical path by a TI (Time Interleaving) block, wherein the time deinterleaver further performs inserting at least one virtual FEC block into at least one TI block of the service data, wherein each TI block includes a variable number of FEC blocks of the service data, wherein a number of the at least one virtual FEC block is defined based on a maximum number of FEC blocks of a TI block and a decoder to decode the time deinterleaved service data.

Output driver architecture with low spur noise
09608681 · 2017-03-28 · ·

In one embodiment, an integrated circuit includes: a first input pad to receive a radio frequency (RF) signal; a radio receiver to process the RF signal and output a digitally processed signal; an analog filter to receive a digital signal via an input signal path and output a drive signal via an output signal path; and a first output pad coupled to the output signal path to output a filtered digital signal based on the drive signal.

Wake up signal for beam tracking
12244390 · 2025-03-04 · ·

Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive, using at least one wake up receiver associated with the UE, one or more wake up signals for beam tracking (WUTs). The UE may measure a quality of each WUT, of the one or more WUTs. The UE may activate a main receiver associated with the UE to perform a beam recovery procedure based at least in part on a measured quality of at least one WUT, of the one or more WUTs. Numerous other aspects are described.

Closed loop multiple transmit, multiple receive antenna wireless communication system

A wireless receiver (74) for receiving signals from a transmitter (72). The transmitter comprises a plurality of transmit antennas (TAT.sub.1, TAT.sub.2) for transmitting the signals, which comprise respective independent streams of symbols. Additionally, interference occurs between the respective streams. The receiver comprises a plurality of receive antennas (RAT.sub.1, RAT.sub.2) for receiving the signals as influenced by a channel effect between the receiver and the transmitter. The receiver also comprises circuitry (80) for multiplying the signals times a conjugate transpose of an estimate of the channel effect and times a conjugate transpose of a linear basis transformation matrix. The receiver also comprises circuitry (84) for selecting the linear basis transformation matrix from a finite set of linear basis transformation matrices. Lastly, the receiver comprises circuitry (88) for removing the interference between the respective streams.

High-speed clock skew correction for SERDES receivers
09548856 · 2017-01-17 · ·

The present invention is directed to data communication. More specifically, the present invention provides a mechanism for determining an adjustment delay that minimizes skew error due to poor alignment between edge samples and data samples. The adjustment delay is determined by sampling edge samples and data samples using different test delays at a calibration frequency that is different from the sampling frequency. The test delay associated with the least average position between the data samples and edge samples is selected as the adjustment delay. The adjustment delay is used as a parameter when sampling data at the sampling frequency. There are other embodiments as well.

Systems and methods for parallel signal cancellation

The present invention provides systems and methods for parallel interference suppression. In one embodiment of the invention, a processing engine is used to substantially cancel a plurality of interfering signals within a received signal. The processing engine includes a plurality of matrix generators that are used to generate matrices, each matrix comprising elements of a unique interfering signal selected for cancellation. The processing engine also includes one or more processors that use the matrices to generate cancellation operators. A plurality of applicators applies the cancellation operators to parallel but not necessarily unique input signals to substantially cancel the interfering signals from the input signals. These input signals may include received signals, interference cancelled signals and/or PN codes.

Data transmission system and receiving device

Provided is a data transmission system, including: a transmitting device configured to transmit a data signal; a receiving device configured to receive the transmitted data signal; and a transmission path for transmitting the data signal, the receiving device including: a detection unit configured to detect a timing at which a polarity of the received data signal is inverted; a plurality of resistors to be selectively connected to a terminal side of the transmission path; and a switching unit configured to switch the plurality of resistors based on the detected timing, the switching unit being configured to select a resistor having a higher resistance value than a characteristic impedance of the transmission path, during a first period, which is a predetermined period from a time point at which the polarity is inverted, and to select, after the first period, a resistor having the same resistance value as the characteristic impedance.

Method and apparatus for identifying co-channel interference

Methods and apparatuses identifying a co-channel interference signal in communications systems are disclosed. An exemplary method comprises generating an interference signal by subtracting a reconstructed desired signal from an at least partially demodulated composite signal, and generating synchronization statistics of interference signal using different scrambling codes. The interference signal is identified as the signal associated with the scrambling code that was used to generate an interference signal having a desired synchronization statistic.