A mixer module includes a mixer, at least one DC offset circuit, a filter and a controller. The mixer mixes an input signal to generate a first signal. The at least one DC offset circuit generates a second signal based on the first signal. The filter filters out an AC portion of the second signal and generates a third signal according to a DC portion of the second signal. The controller controls the at least one DC offset circuit based on the third signal to reduce a DC portion of the first signal.

An apparatus includes a first half-cell, a second half cell and a multiplexer. The first half-cell may comprise a first input stage configured to present a first input signal to a first auto-zero stage. The second half-cell may comprise a second input stage configured to present a second input signal to a second auto-zero stage. The multiplexer may receive a first output from the first auto-zero stage, receive a second output from the second auto-zero stage and present one of the first output and the second output. The first half-cell and the second half-cell may implement a capacitive coupling. The capacitive coupling may provide a rail-to-rail common-mode input range. The first half-cell and the second half-cell may prevent a mismatch between data signals and clock signals. The first half-cell and the second half-cell may each be configured to implement a calibration when idle.

A local oscillator outputs a local oscillation signal. A orthogonal detector subjects a received signal to orthogonal detection by using the local oscillation signal so as to output an I-phase baseband signal and a Q-phase baseband signal. A first HPF and a second HPF reduce a direct current component of each of the I-phase baseband signal and the Q-phase baseband signal. A demodulator demodulates the I-phase baseband signal and the Q-phase baseband signal output from the first HPF and the second HPF. A distribution detector detects an unevenness in a distribution of the I-phase baseband signal and the Q-phase baseband signal with the reduced direct current component. When the distribution detector detects an unevenness in the distribution, the distribution detector changes a status of the first HPF and the second HPF.

A local oscillator outputs a local oscillation signal. A orthogonal detector subjects a received signal to orthogonal detection by using the local oscillation signal so as to output an I-phase baseband signal and a Q-phase baseband signal. A first HPF and a second HPF reduce a direct current component of each of the I-phase baseband signal and the Q-phase baseband signal. A demodulator demodulates the I-phase baseband signal and the Q-phase baseband signal output from the first HPF and the second HPF. A distribution detector detects an unevenness in a distribution of the I-phase baseband signal and the Q-phase baseband signal with the reduced direct current component. When the distribution detector detects an unevenness in the distribution, the distribution detector changes a status of the first HPF and the second HPF.

An apparatus includes a first half-cell, a second half cell and a multiplexer. The first half-cell may comprise a first input stage configured to present a first input signal to a first auto-zero stage. The second half-cell may comprise a second input stage configured to present a second input signal to a second auto-zero stage. The multiplexer may receive a first output from the first auto-zero stage, receive a second output from the second auto-zero stage and present one of the first output and the second output. The first half-cell and the second half-cell may implement a capacitive coupling. The capacitive coupling may provide a rail-to-rail common-mode input range. The first half-cell and the second half-cell may prevent a mismatch between data signals and clock signals. The first half-cell and the second half-cell may each be configured to implement a calibration when idle.

A transceiver that allows dynamic high-pass filter (HPF) cut-off frequency adjustment may include a mixer circuit to mix a local oscillator (LO) signal with a receive (RX) signal received from a transmitter to generate a baseband signal. The transceiver may further include a high-pass filter (HPF) having an adjustable cut-off frequency that is used to reduce a DC offset of the baseband signal. A control circuit can dynamically control components of the HPF to set the adjustable cut-off frequency at a first frequency during a first time period and at a second frequency during a second time period.

A direct current (DC) removal circuit is coupled to a radio-frequency (RF) module, which includes a local oscillator. The DC removal circuit includes: a waveform generator, generating a digital waveform signal having an average value that is smaller than a resolution of a converter coupled to the RF module; a digital adder, coupled to the waveform generator, adding the digital waveform signal to a digital DC value to generate an addition result; and a digital subtractor, subtracting the addition result from a digital signal to generate a subtraction result, so as to compensate leakage caused by the local oscillator.

A current mode end-to-end signal path includes, a digital to analog converter (DAC), operating in current mode and an upconverting mixer, operating in current mode and operatively coupled to the DAC, wherein analog inputs and analog outputs of the DAC and the upconverting mixer are represented as currents, and the DAC generates a baseband signal.

A direct current (DC) offset calibration device and a method are used to calibrate a DC offset of a unit. The DC offset calibration device includes a signal generation unit, a to-be-calibrated unit, a measurement unit, and a compensation unit. The DC offset calibration method includes: using the to-be-calibrated unit to output a clipped signal resulting from a signal saturation effect; receiving a receiving signal correlated to the clipped signal, the receiving signal including an even harmonic resulting from the clipped signal; measuring a magnitude of the even harmonic to obtain a DC offset adjustment value accordingly; and adjusting the to-be-calibrated unit according to the DC offset adjustment value to calibrate the DC offset.

In embodiments of the present disclosure, weighting on a direct current component coefficient dc.sub.i of an I-channel signal and a direct current component coefficient dc.sub.q of a Q-channel signal is performed based on spatial leakage factors k1 and k2 of a microwave chip and a current attenuation amount of a tunable attenuator, to determine a corrected direct current component coefficient dc.sub.i of the I-channel signal and a corrected direct current component coefficient dc.sub.q of the Q-channel signal, and a direct current component superimposed to the I-channel signal of the microwave chip and a direct current component superimposed to the Q-channel signal of the microwave chip are respectively determined based on the corrected direct current component coefficient dc.sub.i of the I-channel signal and the corrected direct current component coefficient dc.sub.q of the Q-channel signal.