A system for phase imbalance calibration, including: an in-phase (I) signal channel including an analog-to-digital converter (ADC) for sampling an I signal to provide a sampled I signal; a quadrature (Q) signal channel including an ADC for sampling a Q signal to provide a sampled Q signal; a sampling clock for controlling the sampling of the ADC on the I signal channel and the sampling of the ADC on the Q signal channel; and sampling clock delay circuitry for adjusting one of a sampling start time of the ADC on the I channel and a sampling start time of the ADC on the Q channel relative to one another such that the sampled I signal and the sampled Q signal are in phase.

A system for phase imbalance calibration, including: an in-phase (I) signal channel including an analog-to-digital converter (ADC) for sampling an I signal to provide a sampled I signal; a quadrature (Q) signal channel including an ADC for sampling a Q signal to provide a sampled Q signal; a sampling clock for controlling the sampling of the ADC on the I signal channel and the sampling of the ADC on the Q signal channel; and sampling clock delay circuitry for adjusting one of a sampling start time of the ADC on the I channel and a sampling start time of the ADC on the Q channel relative to one another such that the sampled I signal and the sampled Q signal are in phase.

A direct current (DC) offset calibration device and a method are used to calibrate a DC offset of a unit. The DC offset calibration device includes a signal generation unit, a to-be-calibrated unit, a measurement unit, and a compensation unit. The DC offset calibration method includes: using the to-be-calibrated unit to output a clipped signal resulting from a signal saturation effect; receiving a receiving signal correlated to the clipped signal, the receiving signal including an even harmonic resulting from the clipped signal; measuring a magnitude of the even harmonic to obtain a DC offset adjustment value accordingly; and adjusting the to-be-calibrated unit according to the DC offset adjustment value to calibrate the DC offset.

In one aspect, an apparatus includes: a low noise amplifier (LNA) to receive and amplify a radio frequency (RF) signal; a mixer coupled to the LNA to downconvert the RF signal to a second frequency signal; a quadrature transimpedance amplifier (TIA) to convert a current of the second frequency signal to a voltage signal, the quadrature TIA having an in-phase (I)-channel having an I-channel DC offset and a quadrature-phase (Q)-channel having a Q-channel DC offset; and a DC offset calibration circuit coupled to the quadrature TIA. The DC offset calibration circuit is configured to calibrate a DC offset of the quadrature TIA. The DC offset calibration circuit may be configured to independently determine an I-channel DC offset setting and independently determine a Q-channel DC offset setting, where the I-channel and Q-channels have a DC offset interdependency.

Faults in a periodically oscillating MEMS mass are detected by processing a position signal, having an amplitude and oscillation frequency, generated as a function of mass position. First and second reference signals formed by samples of quadrature sinusoids at the oscillation frequency are generated. First and second multipliers generate a first product signal and a second product signal, respectively, via multiplication of the position signal by the first and second reference signals. The first and second product signals are low pass filtered to generate first and second filtered signals, respectively. An estimator circuit determines estimates of the amplitude as a function of the first and second filtered signals. A decision circuit detects the presence of faults on the basis of a comparison of the estimates with a range of values.