In some embodiments, a digital clock management system includes input signal conversion circuitry, logic circuitry and output signal conversion circuitry. The input signal conversion circuitry converts input signals to corresponding first digital data streams, each of which contains digital data synchronized to a first data clock. First digital logic circuitry converts the first digital data streams to second digital data streams, each of which contains digital data synchronized to the first data clock, and converts the second digital data streams to third digital data streams, each of which contains digital data synchronized to a common clock. Second digital logic circuitry converts the third digital data streams to a single digital data stream. The output signal conversion circuitry converts the single digital data stream to a modulated output signal.

An electronic device includes a phase locked loop configured to perform a two-point modulation operation on a data signal by using first and second modulation paths, and the phase locked loop is configured to generate, based on a differential value of a first phase error signal generated in the first modulation path, a gain for adjusting a frequency variation of the data signal through the second modulation path so as to match with the frequency variation of the data signal through the first modulation path.

An electronic device includes a phase locked loop configured to perform a two-point modulation operation on a data signal by using first and second modulation paths, and the phase locked loop is configured to generate, based on a differential value of a first phase error signal generated in the first modulation path, a gain for adjusting a frequency variation of the data signal through the second modulation path so as to match with the frequency variation of the data signal through the first modulation path.

The present disclosure relates to a method for up-converting a clock signal, a clock circuit and a digital processing device. More specifically, provided is a method for up-converting a clock signal, comprising: employing a first clock sub-circuit to provide a clock signal having a first frequency to a chip; receiving an instruction to up-convert the clock signal having the first frequency to a clock signal having a second frequency; in response to receiving the instruction, causing a second clock sub-circuit to output the clock signal having the second frequency; and after the second clock sub-circuit outputs the clock signal having the second frequency, employing the second clock sub-circuit to provide the clock signal having the second frequency to the chip in place of the first clock sub-circuit.

Embodiments of the present invention synchronize multiple synthesizers, such as phase-locked loops (PLLs), in a manner that does not require communication or coordination between the synthesizers. Specifically, each synthesizer is part of a synthesizer circuit that includes a synthesizer (e.g., a PLL), a phase measurement circuit, and a synchronization circuit. A common reference signal (e.g., an alternating clock signal) is provided to the synthesizer circuits. In one exemplary embodiment, in each synthesizer circuit, the phase measurement circuit measures a phase difference between the reference signal and a corresponding output of the synthesizer, and the synchronization circuit adjusts the synthesizer operation based on the measured phase difference in such a way that all of the synthesizers operate in-phase with one another relative to the common reference signal, without having any communication or coordination between the two synthesizer circuits other than provision of the common reference signal.

Clock recovery from a serial data signal involves using a serializer/deserializer (SERDES) to produce a clock signal which periodically alternates between high and low output clock values. These high and low clock values are generated by outputting for each clock period a series of N digital bits including a plurality of low-level bits to form each low output clock value and a plurality of high-level bits to form each high output clock value. A sync pulse obtained from a sync word present in each frame of the serial data signal is used to periodically determine a frequency error of the clock signal. The frequency error is used as a basis to change a phase of the adjusted clock signal responsive to the frequency error.

A clock recovery circuit a first phase-locked loop (PLL) circuit configured to perform a coarse phase fixing operation on a test data signal by using a first reference clock signal, the test data signal having a prescribed pattern, and a second PLL circuit configured to perform a fine phase fixing operation on the test data signal, subsequently to the coarse phase fixing operation. The second PLL circuit may be configured to perform the fine phase fixing operation on the test data signal by selectively using at least two selection reference clock signals among a plurality of second reference clock signals that are delayed from the first reference clock signal by a unit phase, in a training mode, having a phase difference of N times the unit phase, where N is an integer equal to or greater than 2.

This disclosure relates to a receiver that includes a clock and data recovery loop and a phase offset loop. The clock and data recovery loop may be controlled by a sum of gradients for a plurality of data interleaves. The phase offset loop may be controlled by an accumulated differential gradient for each of the data interleaves.

When digital input data disappear temporarily, within a counting period of the counter and pulse generator, an output voltage of the voltage generator rises, a threshold detector compares the output voltage of the voltage generator with a plurality of threshold values to generate a plurality of comparison results, and a logic gate unit generates a control signal according to the comparison results, to a charge pump, so that the charge pump controls the voltage-controlled oscillator to accelerate or decelerate.

A phase locked loop (PLL) method includes generating a first signal based on a comparison of a phase of a reference clock or signal to a phase of a feedback clock; generating an output clock based on the first signal; generating an intermediate feedback clock including frequency dividing the output clock; fractionally frequency dividing the intermediate feedback clock based on a digital control signal to generate the feedback clock; and generating the digital control signal based on a sampling clock having a frequency greater than a frequency of the feedback clock. In one implementation, a PLL includes a frequency multiplier to generate the sampling clock based on the feedback clock. In another implementation, a PLL uses the intermediate feedback clock as the sampling clock.