A multi-mode processing circuit and a multi-mode controlling method thereof are provided. The multi-mode processing circuit includes, but is not limited to, a control circuit and a mixer. The control circuit is configured to receive an input signal and output one of a control signal and another control signal according to the input signal. The mixer is coupled to the control circuit and is configured to mix the control signal output by the control circuit with another input signal or mix the other control signal with the another input signal to output an output signal. Accordingly, the mixer and a buffer can be integrated into a single cell, and a fast mode switch can be achieved.

The invention relates to a mixer circuit, which includes a transconductance stage circuit, a switch stage circuit and a load stage circuit which are electrically connected in sequence. The transconductance stage circuit is used to access a radio frequency voltage signal and convert the radio frequency voltage signal into a radio frequency current signal The switch-level circuit is used to access the local oscillator signal and the radio frequency current signal, and the switch-level transistor is turned on by using the local oscillator signal; the load-level circuit is used to convert the intermediate frequency current signal into a voltage signal for output. In the present invention, the transconductance stage circuit adopts a transistor superposition technology structure, which improves the conversion gain of the mixer; at the same time, it uses a source degenerate inductance structure, which further improves the conversion gain and linearity of the circuit.

An image rejection mixer includes a delay circuit for delaying one of first signals divided by a distribution circuit and a second signal provided to a second mixing circuit by the same delay amount d, or delaying the other one of the first signals divided by the distribution circuit and the second signal provided to a first mixing circuit by the same delay amount d.

The invention relates to a mixer circuit, which includes a transconductance stage circuit, a switch stage circuit and a load stage circuit which are electrically connected in sequence. The transconductance stage circuit is used to access a radio frequency voltage signal and convert the radio frequency voltage signal into a radio frequency current signal The switch-level circuit is used to access the local oscillator signal and the radio frequency current signal, and the switch-level transistor is turned on by using the local oscillator signal; the load-level circuit is used to convert the intermediate frequency current signal into a voltage signal for output. In the present invention, the transconductance stage circuit adopts a transistor superposition technology structure, which improves the conversion gain of the mixer; at the same time, it uses a source degenerate inductance structure, which further improves the conversion gain and linearity of the circuit.

An electronic circuit including: a differential multiplier circuit with a first differential input and a second differential input and a differential output; and a phase locked loop (PLL) circuit including: (1) a balanced differential mixer circuit with a first differential input electrically connected to the differential output of the differential multiplier circuit, a second differential input, and an output; (2) a loop filter having an output and an input electrically connected to the output of the balanced differential mixer circuit; and (3) a voltage controlled oscillator (VCO) circuit having an input electrically connected to the output of the loop filter and with an output electrically feeding back to the second differential input of the balanced differential mixer circuit.

The disclosed embodiments relate to the design of a system that implements an up-conversion mixer. This system includes a regulator-based linearized transconductance (g.sub.m) stage, which converts a differential intermediate frequency (IF) voltage signal into a corresponding pair of IF currents. It also includes a pair of current mirrors, which duplicates the pair of IF currents into sources of a set of switching transistors. The set of switching transistors uses a differential local oscillator (LO) signal to gate the duplicated pair of IF currents to produce a differential radio frequency (RF) output signal. Finally, a combination of capacitors and/or inductors is coupled to common source nodes of the set of switching transistors to suppress higher order harmonics in an associated common source node voltage signal.

An electronic circuit including: a differential multiplier circuit with a first differential input and a second differential input and a differential output; and a phase locked loop (PLL) circuit including: (1) a balanced differential mixer circuit with a first differential input electrically connected to the differential output of the differential multiplier circuit, a second differential input, and an output; (2) a loop filter having an output and an input electrically connected to the output of the balanced differential mixer circuit; and (3) a voltage controlled oscillator (VCO) circuit having an input electrically connected to the output of the loop filter and with an output electrically feeding back to the second differential input of the balanced differential mixer circuit.

A down-conversion mixer includes a converting-and-mixing module and a load module. The converting-and-mixing module performs voltage-to-current conversion and mixing with first and second differential oscillatory voltage signal pairs upon a differential input voltage signal pair to generate first and second differential mixed current signal pairs. The load module includes two RL circuits and a negative resistance providing circuit that cooperate to convert the first and second differential mixed current signal pairs into first and second differential mixed voltage signal pairs. Each RL circuit includes two variable resistors, and an inductor connected between the variable resistors.

The disclosed embodiments relate to the design of a system that implements an up-conversion mixer. This system includes a regulator-based linearized transconductance (g.sub.m) stage, which converts a differential intermediate frequency (IF) voltage signal into a corresponding pair of IF currents. It also includes a pair of current mirrors, which duplicates the pair of IF currents into sources of a set of switching transistors. The set of switching transistors uses a differential local oscillator (LO) signal to gate the duplicated pair of IF currents to produce a differential radio frequency (RF) output signal. Finally, a combination of capacitors and/or inductors is coupled to common source nodes of the set of switching transistors to suppress higher order harmonics in an associated common source node voltage signal.

An electronic circuit including: a differential multiplier circuit with a first differential input and a second differential input and a differential output; and a phase locked loop (PLL) circuit including: (1) a balanced differential mixer circuit with a first differential input electrically connected to the differential output of the differential multiplier circuit, a second differential input, and an output; (2) a loop filter having an output and an input electrically connected to the output of the balanced differential mixer circuit; and (3) a voltage controlled oscillator (VCO) circuit having an input electrically connected to the output of the loop filter and with an output electrically feeding back to the second differential input of the balanced differential mixer circuit.