A harmonic mixer that suppresses the degradation of the conversion efficiency is disclosed. That harmonic mixer includes an input transmission line, an output transmission line, and two transistors connected in parallel between the input transmission line and the output transmission line. Two transistors are complementarily driven by a local signal LO and generate an output signal RF with frequencies of 2f.sub.LOf.sub.IF, where f.sub.LO and f.sub.IF are frequencies of a local signal LO and an intermediate signal IF.

A configurable passive mixer is described herein. According to one exemplary embodiment, a passive mixer for a wireless receiver comprises a plurality of passive mixer cores coupled in parallel with each mixer core configured to receive a same set of radio frequency input signals and a separately driven set of local oscillator input signals. Further, each mixer core is configured to be separately enabled or disabled so that the passive mixer can be selectively configured during operation to convert the same set of radio frequency input signals to a set of downconverted output signals that satisfy a certain performance requirement or performance parameter of the passive mixer.

One embodiment described is an apparatus that includes an active device structured in a semiconductor body. The semiconductor body may include a gate terminal to receive a switched bias signal, and a bulk terminal to receive a forward body-bias signal. A first circuit portion may be coupled to the gate terminal to provide the switched bias signal, and a second circuit portion may be coupled to the bulk terminal to provide the forward body-bias signal.

Embodiments are provided for biasing circuits with compensation of process variation without band-gap referenced current or voltage. In an embodiment, a circuit for biasing a field-effect transistor (FET) passive mixer comprises a series of diode-connected FETs, and a series of first resistors connected to a voltage source and the series of diode-connected FETs. Additionally, one or more second resistors are connected to the series of diode-connected FETs and to ground. In an embodiment method, the total number of the diode-connected FETs and the total number of the resistors, including the first and second series of resistors, are selected. The total number of the second resistors is then determined according to a defined relation between the selected total number of diode-connected FETs and the total number of resistors.

A harmonic mixer that suppresses the degradation of the conversion efficiency is disclosed. That harmonic mixer includes an input transmission line, an output transmission line, and two transistors connected in parallel between the input transmission line and the output transmission line. Two transistors are complementarily driven by a local signal LO and generate an output signal RF with frequencies of 2f.sub.LOf.sub.IF, where f.sub.LO and f.sub.IF are frequencies of a local signal LO and an intermediate signal IF.

An apparatus is disclosed for oscillator leakage calibration. In example aspects, the apparatus includes a mixer circuit and calibration circuitry. The mixer circuit has a first stage including at least one transistor coupled between a mixer input and a mixer output and a second stage including one or more transistors coupled between the at least one transistor and the mixer output. The mixer circuit also has tuning circuitry coupled to the at least one transistor. The calibration circuitry includes at least one resistor coupled between a power distribution node and at least one mixer node, with the at least one mixer node coupled between the at least one transistor and the one or more transistors, and at least one switch coupled between the power distribution node and the at least one mixer node. The calibration circuitry also includes controller circuitry coupled between the mixer node and the tuning circuitry.

Certain aspects of the present disclosure provide techniques and circuits for frequency mixing signals. One example circuit generally includes a transformer comprising a primary winding and a secondary winding, the transformer configured to generate a signal across the secondary winding based on a signal at an input node coupled to the primary winding, and a first mixer coupled to the secondary winding of the transformer and configured to convert a frequency of the signal across the secondary winding. In certain aspects, the circuit also includes a biasing circuit having an output coupled to a tap of the secondary winding and configured to generate a biasing voltage by applying an offset voltage to a common-mode voltage of the first mixer and apply the biasing voltage to the tap of the secondary winding to bias the first mixer.

Mixer circuitry can include a first pair of transistors coupled to a first tail node and configured to receive a local oscillator signal, a second pair of transistors coupled to a second tail node and configured to receive the local oscillator signal, a first digital-to-analog converter, a second DAC coupled between the first DAC and of the first pair of transistors, and a third DAC coupled between the first DAC and the second pair of transistors. During a first phase, control circuitry can sweep the first DAC to trim a first and/or other odd order local oscillator feedthrough. During a second phase, the control circuitry can sweep the second DAC to trim a second and/or other even order local oscillator feedthrough. During a third phase, the control circuitry can sweep the second and third DACs to reject signals associated with a second harmonic conversion gain of the mixer circuitry.

Mixer circuitry can include a first pair of transistors coupled to a first tail node and configured to receive a local oscillator signal, a second pair of transistors coupled to a second tail node and configured to receive the local oscillator signal, a first digital-to-analog converter, a second DAC coupled between the first DAC and of the first pair of transistors, and a third DAC coupled between the first DAC and the second pair of transistors. During a first phase, control circuitry can sweep the first DAC to trim a first and/or other odd order local oscillator feedthrough. During a second phase, the control circuitry can sweep the second DAC to trim a second and/or other even order local oscillator feedthrough. During a third phase, the control circuitry can sweep the second and third DACs to reject signals associated with a second harmonic conversion gain of the mixer circuitry.