A receiver may receive a signal and process each of a plurality of sub-bands of the received signal via a respective one of a plurality of first-type receive chains. The receiver may utilize a signal output by a first one of the plurality of the first-type receive chains to remove undesired signals from a signal output by a second one of the plurality of the first-type receive chains. The undesired signals may comprise aliases and/or harmonics of one or more signals that fall within a sub-band of the first one of the plurality of the first-type receive chains. The receiver may downconvert, filter, and digitize each of the plurality of sub-bands via a corresponding one of the plurality of the first type receive chains. The received signal may encompass the cable television band, and each of the plurality of sub-bands may comprise a plurality of cable television channels.

A receiver may receive a signal and process each of a plurality of sub-bands of the received signal via a respective one of a plurality of first-type receive chains. The receiver may utilize a signal output by a first one of the plurality of the first-type receive chains to remove undesired signals from a signal output by a second one of the plurality of the first-type receive chains. The undesired signals may comprise aliases and/or harmonics of one or more signals that fall within a sub-band of the first one of the plurality of the first-type receive chains. The receiver may downconvert, filter, and digitize each of the plurality of sub-bands via a corresponding one of the plurality of the first type receive chains. The received signal may encompass the cable television band, and each of the plurality of sub-bands may comprise a plurality of cable television channels.

A circuit for demodulating an input signal is described. The circuit may be configured to demodulate signals modulated with amplitude-based modulation schemes, such as amplitude shift keying (ASK). The demodulator may comprise a clock extractor configured to generate a clock signal in response to receiving an amplitude-modulated input signal, a phase shifter configured to generate a sampling signal by phase-shifting the clock signal by approximately /2, and a sampler configured to sample the input signal in correspondence to one or more edges (such as one or more falling edges) of the sampling signal. In this way, the amplitude-modulated input signal may be sampled at its peak, or at least near its peak, thus ensuring high signal fidelity.

A receiver may receive a signal and process each of a plurality of sub-bands of the received signal via a respective one of a plurality of first-type receive chains. The receiver may utilize a signal output by a first one of the plurality of the first-type receive chains to remove undesired signals from a signal output by a second one of the plurality of the first-type receive chains. The undesired signals may comprise aliases and/or harmonics of one or more signals that fall within a sub-band of the first one of the plurality of the first-type receive chains. The receiver may downconvert, filter, and digitize each of the plurality of sub-bands via a corresponding one of the plurality of the first type receive chains. The received signal may encompass the cable television band, and each of the plurality of sub-bands may comprise a plurality of cable television channels.

The disclosure relates to a module for a radio receiver. The module comprises an input terminal; an output terminal; a main signal path for communicating in-phase and quadrature signals between the input terminal and the output terminal; and a second signal path. The second signal path is connected in parallel with the main signal path and is configured to: extract in-phase and quadrature signals from the main signal path; filter the extracted in-phase and quadrature signals; detect an error in the filtered, extracted in-phase and quadrature signals; and apply a correction to in-phase and quadrature signals on the main signal path based on the error.

An apparatus and method. The method includes filtering an output of an in-phase (I-mixer); filtering an output of a quadrature-mixer (Q-mixer); converting an output of a first low pass filter (LPF); converting an output of a second LPF; buffering an output of a first analog-to-digital converter (ADC); buffering an output of a second ADC; buffering a transmitter signal; generating a reference signal from an output of a transmitter (TX) data capture buffer; removing DC from the reference signal; and adaptively tuning an I-mixer digital-to-analog (DAC) code and a Q-mixer DAC code from an output of a first receiver (RX) data capture buffer, an output of a second RX data capture buffer, an output of a DC removal unit, and a predetermined step size for each of the I-mixer DAC code and the Q-mixer DAC code.

According to an embodiment, a circuit is proposed for generating rate and quadrature demodulation signals, incorporating unidirectional hysteresis for negative edges. The circuit features a preliminary stage that amplifies the differential sinusoidal signal from gyroscopic proof mass oscillations; a gain stage for boosting this signal with adjustable hysteresis levels; an output stage delivering a full-swing square wave output; and a customizable offset component to deepen the drop in the non-inverting compared to the inverting signal for the third signal's falling edge.

According to an embodiment, a circuit is proposed for generating rate and quadrature demodulation signals, incorporating unidirectional hysteresis for negative edges. The circuit features a preliminary stage that amplifies the differential sinusoidal signal from gyroscopic proof mass oscillations; a gain stage for boosting this signal with adjustable hysteresis levels; an output stage delivering a full-swing square wave output; and a customizable offset component to deepen the drop in the non-inverting compared to the inverting signal for the third signal's falling edge.

In a digital envelope detector circuit, an input terminal receives a digital input signal and an output terminal produces a digital output signal. First and second digital processing circuitry between the input and output terminals each includes a memory element. The first processing circuitry applies low-pass filtering to the digital input signal. The second processing circuitry processes the digital input signal, stores in the memory element a value indicative of the processed digital input signal, and processes the output from the memory element so that the digital input signal is passed unaltered. A digital comparator circuit compares the digital input and output signals, asserts a control signal in response to the digital input signal being higher, and de-asserts the control signal in response to the digital input signal being lower. The first/second processing circuitry produces the digital output signal in response to the control signal being de-asserted/asserted.