Frequency domain (FDTF) and time domain (TDTF) trans-filters compress in-band AWGN, demodulate input signals and have no threshold due to applied noise. Two parallel frequency selective networks with opposite amplitude vs frequency slopes are designed to remain 180 degrees out of phase over the signal band in the FDTF whereas two parallel delay networks are used in the TDTF. Output amplitudes are equal at band center and are summed producing a monotonic amplitude vs frequency characteristic going thru zero at center frequency with abrupt phase reversal. This produces the parabolic output noise density and differentiates applied signals. Absence of nonlinear circuit components and product devices prevents generation of noisenoise products, avoiding the threshold phenomenon. Exponentially modulated digital signals produce output impulses due to the slope and abrupt phase reversal. The impulses have strong fundamental frequency components and may be recovered at baseband without frequency conversion. Cascading trans-filters increases noise reduction and impulse amplitude. The trans-filter algorithm may be used separately or in conjunction with one or more hardware trans-filters.

Trans-filter/Detectors are extremely sensitive circuits that recover exponentially modulated signals buried in noise. They can be used wherever Matched Filter/Coherent Detectors are used and operate at negative input signal-to-noise ratios to recover RADAR, SONAR, communications, or data signals, as well as reduce phase noise of precision oscillators. Input signal and noise is split into two paths where complementary derivatives are extracted. Outputs of the two paths are equal in amplitude and 180 degrees relative to each other at the band center frequency. The outputs are summed, causing stationary in-band noise to be reduced by cancellation while exponentially modulated signals are undiminished. Trans-filters are Linear Time Invariant circuits, have no noise x noise threshold and can be cascaded, increasing output signal-to-noise ratio prior to detection. Trans-filters are most sensitive to all types of digital modulation, producing easily detected polarized pulses synchronous with data transitions. Trans-filters do not require coherent conversion oscillators and complex synchronizing circuits.

Frequency domain (FDTF) and time domain (TDTF) trans-filters compress in-band AWGN, demodulate input signals and have no threshold due to applied noise. Two parallel frequency selective networks with opposite amplitude vs frequency slopes are designed to remain 180 degrees out of phase over the signal band in the FDTF whereas two parallel delay networks are used in the TDTF. Output amplitudes are equal at band center and are summed producing a monotonic amplitude vs frequency characteristic going thru zero at center frequency with abrupt phase reversal. This produces the parabolic output noise density and differentiates applied signals. Absence of nonlinear circuit components and product devices prevents generation of noisenoise products, avoiding the threshold phenomenon. Exponentially modulated digital signals produce output impulses due to the slope and abrupt phase reversal. The impulses have strong fundamental frequency components and may be recovered at baseband without frequency conversion. Cascading trans-filters increases noise reduction and impulse amplitude. The trans-filter algorithm may be used separately or in conjunction with one or more hardware trans-filters.

In a digital envelope detector circuit, an input terminal receives a digital input signal and an output terminal produces a digital output signal. First and second digital processing circuitry between the input and output terminals each includes a memory element. The first processing circuitry applies low-pass filtering to the digital input signal. The second processing circuitry processes the digital input signal, stores in the memory element a value indicative of the processed digital input signal, and processes the output from the memory element so that the digital input signal is passed unaltered. A digital comparator circuit compares the digital input and output signals, asserts a control signal in response to the digital input signal being higher, and de-asserts the control signal in response to the digital input signal being lower. The first/second processing circuitry produces the digital output signal in response to the control signal being de-asserted/asserted.