Patent classifications
H03F1/083
QUADRATURE ERROR CORRECTION FOR RADIO TRANSCEIVERS
Quadrature error correction (QEC) for radio transceivers are provided herein. In certain embodiments, a transceiver includes an in-phase (I) signal path including a first controllable amplifier coupled to a first data converter, and a quadrature-phase (Q) signal path including a second controllable amplifier coupled to a second data converter. The transceiver further includes a QEC circuit operable to correct for a quadrature error between the I signal path and the Q signal path by adjusting a gain of the first controllable amplifier and/or a gain of the second controllable amplifier.
OPTO-ELECTRONIC ASSEMBLIES
An assembly of electronic components for reception of data using an optical fibre wherein said assembly comprises: a photodiode; a first amplifier coupled to said photodiode; a second amplifier, whose electrical behaviour is substantially identical to an electrical behaviour of said first amplifier; an impedance network comprising at least two electronic components coupled between an input of said second amplifier and a reference terminal, wherein those at least two electronic components comprise at least two impedance elements, one impedance element being capacitive and another being resistive or inductive, and wherein said at least two electronic components are adjustable under electronic control to adjust the impedance presented by said impedance network; and circuitry for creating a signal formed from a subtraction of outputs of the first and second amplifiers.
Sensor interface including resonator and differential amplifier
Provided is a sensor interface including a first cantilever beam bundle including at least one resonator and a first output terminal, a second cantilever beam bundle including at least one resonator and a second output terminal, and a differential amplifier including a first input terminal electrically connected to the first output terminal of the first cantilever beam bundle and a second input terminal electrically connected to the second output terminal of the second cantilever beam bundle.
Broadband, high-efficiency, non-modulating power amplifier architecture
Apparatus and methods for a no-load-modulation power amplifier are described. No-load-modulation power amplifiers can comprise multiple amplifiers connected in parallel to amplify a signal that has been divided into parallel circuit branches. One of the amplifiers can operate as a main amplifier in a first amplification class and the remaining amplifiers can operate as peaking amplifiers in a second amplification class. The main amplifier can see essentially no modulation of its load between the power amplifier's fully-on and fully backed-off states. The power amplifiers can operate in symmetric and asymmetric modes. Improvements in bandwidth and drain efficiency over conventional Doherty amplifiers are obtained. Further improvements can be obtained by combining signals from the amplifiers with hybrid couplers.
OPERATIONAL AMPLIFIER
An operational amplifier 1 comprises transistors Q1 and Q2 forming an input stage, and input resistors R1 and R2 which form a filter together with parasitic capacitors C1 and C2 accompanying the transistors Q1 and Q2. Resistance values R of the resistors R1 and R2 may be set to R=1/(2π.Math.fc.Math.C), where C is the capacitance value of each of the parasitic capacitors C1 and C2, and fc is the target cutoff frequency of the filter. The operational amplifier 1 may also include a power supply resistor R0 which forms a filter together with a parasitic capacitor C0 accompanying a power supply line.
Trans-Impedance Amplifier, Chip, and Communications Device
A trans-impedance amplifier (TIA) includes a first circuit, a second circuit, and a third circuit. Both the first circuit and the second circuit are coupled to a current source, an operational amplifier, and the third circuit. The first circuit is configured to receive a first current, provide a third voltage to the third circuit, perform shape filtering on the first current, and convert the shape filtered first current to a first voltage for output. The second circuit is configured to receive a second current, provide a fourth voltage to the third circuit, perform shape filtering on the second current, and convert the shape filtered second current to a second voltage for output. The third circuit is configured to cooperate with the first circuit and the second circuit in performing shape filtering. The operational amplifier is configured to provide a small-signal virtual ground point to the first circuit.
Method for noise reduction and a detection circuit
A method and a detection circuit. The detection circuit may include (a) a photodiode that is configured to convert radiation to a photodiode current; (b) a photodiode bias circuit that is configured to bias the photodiode; (c) a dynamic resistance circuit that has a first terminal and a second terminal; (d) a transimpedance amplifier that is configured to amplify an output current of the dynamic resistance circuit to provide an output voltage, wherein the second terminal is coupled to a negative input port of the amplification circuit; and (e) a conductor that is coupled between the first terminal and an anode of the photodiode.
Transimpedance circuits and methods
Disclosed herein are transimpedance circuits, as well as related methods and devices. In some embodiments, a transimpedance circuit may include a current source bias terminal, a current source output terminal, and a transimpedance amplifier coupled to the current source output terminal, wherein voltage signals at the current source bias terminal are correlated with voltage signals at the current source output terminal. In some embodiments, the current source may be a photodiode.
AMPLIFIER
The present application discloses an amplifier, including: a positive-end PMOS; a negative-end PMOS; a positive-end NMOS, having a drain coupled to a drain of the positive-end PMOS and outputting a positive-end output signal; a negative-end NMOS, having a drain coupled to a drain of the negative-end PMOS and outputting a negative-end output signal; a first resistor, coupled between a gate of the negative-end NMOS and a negative-end input signal; a second resistor, coupled between a gate of the negative-end NMOS and the positive-end output signal; a third resistor, coupled between a gate of the negative-end PMOS and the negative-end input signal; and a fourth resistor, coupled between a gate of the negative-end PMOS and the positive-end output signal.
LOW NOISE TRANS-IMPEDANCE AMPLIFIER
A new trans-impedance amplifier (TIA) with low noise is provided. The TIA may include an input stage and an output driving stage. The input stage may include a pair of input PMOS transistors, a pair of input NMOS transistors, and a pair of differential voltage input nodes. The output driving stage may include a pair of output circuits, each may include a first pair of PMOS and NMOS transistors electrically connected in parallel, a second pair of PMOS and NMOS transistors electrically connected in series, and a pair of capacitors electrically connected in series, which are electrically connected in parallel. The structure can lead to a reduced noise level of the TIA.