A radio frequency circuit includes a power amplifier configured to selectively amplify one of a first radio frequency signal and a second radio frequency signal that have different bandwidths, and when the first radio frequency signal is input to the power amplifier, a first bias signal is applied to the power amplifier, and when the second radio frequency signal is input to the power amplifier, a second bias signal different from the first bias signal is applied to the power amplifier.

A two-stage differential amplifier with cross-coupled compensation capacitors. The differential amplifier includes first amplifier circuitry receiving a differential input voltage and presenting first and second intermediate outputs. The amplifier further includes a second amplifier stage with a first leg having an input coupled to the second intermediate output of the first amplifier circuitry, and a second leg having an input coupled to the first intermediate output of the first amplifier circuitry. A compensation capacitor is provided for each leg of the second amplifier stage, each coupled between the output of that amplifier leg and its input. A first cross-coupled capacitor is coupled between the output of the first amplifier leg to the input of the second amplifier leg, and a second cross-coupled capacitor is coupled between the output of the second amplifier leg and the input of the first amplifier leg.

According to an embodiment, an operational amplifier includes a first amplifier stage coupled between an input node and an intermediate node, a second amplifier stage coupled between the intermediate node and an output node, a compensation capacitor having a first terminal coupled to the intermediate node and a second terminal, and a compensation amplifier coupled between the output node and the second terminal. The compensation amplifier has a positive gain greater than one.

An amplifier circuit includes source-grounded amplifiers and a neutralization circuit that is connected between drain terminals and gate terminals of the source-grounded amplifiers and neutralizes a feedback capacitance of the source-grounded amplifiers, and the neutralization circuit includes transmission lines and a capacitor connected in series.

An amplifier circuit includes source-grounded amplifiers and a neutralization circuit that is connected between drain terminals and gate terminals of the source-grounded amplifiers and neutralizes a feedback capacitance of the source-grounded amplifiers, and the neutralization circuit includes transmission lines and a capacitor connected in series.

An amplifier circuit having low parasitic pole effect includes a preamplifier, an output transistor and a buffer circuit. The buffer circuit generates a driving signal to control the output transistor according to a preamplification signal generated by the preamplifier. The buffer circuit includes: a buffer input transistor generating the driving signal, wherein an input impedance at its control end is less than that of the output transistor; a low output impedance circuit having an output impedance which is less than an inverting output impedance of the buffer input transistor; an amplification transistor generating an amplification signal at its inverting output; and an amplification stage circuit amplifying the amplification signal by an amplification ratio, so that an equivalent output impedance at a non-inverting output of the buffer input transistor is less than or equal to a product of the reciprocal of an intrinsic output impedance thereof and an amplification ratio.

An amplifier circuit having low parasitic pole effect includes a preamplifier, an output transistor and a buffer circuit. The buffer circuit generates a driving signal to control the output transistor according to a preamplification signal generated by the preamplifier. The buffer circuit includes: a buffer input transistor generating the driving signal, wherein an input impedance at its control end is less than that of the output transistor; a low output impedance circuit having an output impedance which is less than an inverting output impedance of the buffer input transistor; an amplification transistor generating an amplification signal at its inverting output; and an amplification stage circuit amplifying the amplification signal by an amplification ratio, so that an equivalent output impedance at a non-inverting output of the buffer input transistor is less than or equal to a product of the reciprocal of an intrinsic output impedance thereof and an amplification ratio.

A reactance cancelling radio frequency (RF) circuit array is disclosed. The reactance cancelling RF circuit array includes multiple RF circuits each coupled to one or two adjacent RF circuits by one or two pairs of coupling mediums each having a respective length less than one-quarter wavelength. In one aspect, an RF input signal is first split across the RF circuits and then combined to form an RF output signal. As a result, each RF circuit requires a lower power handling capability to process a portion of the RF input signal. In another aspect, each pair of the coupling mediums can cause reactance cancellation in each reactance-cancelling pair of the RF circuits. By coupling the RF circuits via the coupling mediums and enabling splitting-combining among the RF circuits, it is possible to miniaturize the reactance cancelling RF circuit array for improved performance across a wide frequency spectrum.

A wave shaping circuit reduces slope magnitudes during increasing and decreasing voltage transitions. The wave shaping circuit includes a first switch that receives an input voltage having at least two voltage values where an input voltage transition between the at least two voltage values has a first slope magnitude; an inductor connected in series with the first switch; a second switch connected in a parallel arrangement with the first switch and the inductor; and a capacitor having a first end connected between the inductor and an output port and a second end connected to ground. When the input voltage begins the input voltage transition to a higher voltage value, the first switch turns on and the second switch turns off, such that the inductor limits current flow from the input voltage, decreasing a second slope magnitude of an output voltage transition to less than the first slope magnitude.

An amplifier circuit with a differential input and a differential output comprises a first and a second pair of matched transistors having a first threshold voltage and comprising control terminals connected to the differential input. A first and a second pair of triplets of transistors having a second threshold voltage being different from the first threshold voltage is connected to each one of the pairs of matched transistors such that respective current paths are formed with these transistors. The currents are split up to bias current sources and to an output stage such that the current is reused for implementing a class AB operation. Furthermore, a current through bias transistors connected in the current path of the first and the second pair of matched transistors is mirrored to output transistors being arranged in a differential current path of the output stage.