A power amplifier apparatus includes a semiconductor substrate, a plurality of first transistors on the semiconductor substrate, a plurality of second transistors, at least one collector terminal electrically connected to collectors of the plurality of first transistors, a first inductor having a first end electrically connected to the collector terminal and a second end electrically connected to a power supply potential, at least one emitter terminal electrically connected to emitters of the plurality of second transistors and adjacent to the collector terminal in a second direction, a second inductor having a first end electrically connected to the emitter terminal and a second end electrically connected to a reference potential, and at least one capacitor having a first end electrically connected to the collectors of the plurality of first transistors and a second end electrically connected to the emitters of the plurality of second transistors.

A dc coupled amplifier includes a pre-driver, and amplifier and a bias control circuit. The pre-driver is configured to receive one or more input signals and amplify the one or more input signals to create one or more pre-amplified signals. The amplifier has cascode configured transistors configured to receive and amplify the one or more pre-amplified signals to create one or more amplified signals, the amplifier further having an output driver termination element. The bias control circuit is connected between the pre-driver and the amplifier, the bias control circuit receiving at least one bias current from the output driver termination element of the amplifier, wherein the pre-driver, the amplifier and the bias control circuit are all formed on a same die.

A front end module (FEM) integrated circuit (IC) architecture that uses the same LNA in each of several frequency bands extending over a wide frequency range. In some embodiments, switched impedance circuits distributed throughout the front end circuit allow selection of the frequency response and impedances that are optimized for particular performance parameters targeted for a desired device characteristic. Such switched impedance circuits tune the output and input impedance match and adjust the gain of the LNA for specific operating frequencies and gain targets. In addition, adjustments to the bias of the LNA can be used to optimize performance trade-offs between the total direct current (DC) power dissipated versus radio frequency (RF) performance. By selecting appropriate impedances throughout the circuit using switched impedance circuits, the LNA can be selectively tuned to operate optimally at a selected bias for operation within selected frequency bands.

Methods and systems for a multi gain LNA architecture achieving minimum phase discontinuity between all the different active and passive gain modes that uses different LNA configurations and settings for single and multi-stage LNAs by a configurable combined output matching and phase adjusting circuitry.

A TX/RX switch includes a power amplifier (PA), a Low Noise Amplifier (LNA), and an antenna connection. The PA is connected to a PA matching network that has a PA network impedance and a common PA-LNA impedance connected in one or more series-parallel combinations in different embodiments in a transmitting mode. The LNA is connected to a LNA matching network that has a LNA network impedance and the same common PA-LNA impedance connected in one or more series-parallel combinations in a receive mode. A mode switch can connect the common PA-LNA impedance in different configurations to enable the transmitting and receiving mode respectively. In some embodiments, the mode switch can short or open circuit the connection of the PA matching circuit or the LNA matching circuit to the antenna. In some embodiments, the mode switch can also turn power on or off to the PA or the LNA when the switch is in a mode where the respective amplifier is not selected. Accordingly, with specific design limitations on the common PA-LNA impedance combined with different mode switch configurations of the TX/RX switch components in either the TX or RX mode, the TX/RX switch operates within a design bandwidth without transmission lines embedded in the TX/RX switch circuitry and provides optimum power transfer from/to the antenna at the antenna connection with reduced noise.

Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit standby current during operation in the standby mode while allowing a quick recovery to normal operating conditions of the amplifier. Biasing an input transistor of the stacked transistors can be obtained by using a replica stack circuit.

A transistor stack can include a combination of floating and body tied devices. Improved performance of the RF amplifier can be obtained by using a single body tied device as the input transistor of the stack, or as the output transistor of the stack, while other transistors of the stack are floating transistors. Transient response of the RF amplifier can be improved by using all body tied devices in the stack.

A transistor comprises a drain, a gate, a source, a body terminal and a body resistance. The drain is connected to a supply voltage line to receive a supply voltage. The gate is connected to a control voltage line to receive a control voltage. The source is connected to a input line to receive a input radio frequency signal. The body terminal is connected to the drain. The body resistance is disposed between the drain and the body terminal. By the foregoing configuration, the leakage current of the substrate is reduced and the threshold voltage of the transistor is reduced to conform to the present low power design.

Disclosed herein are methods for use in operating signal amplifiers that provide impedance adjustments for different gain modes. The impedance adjustments are configured to result in a constant real impedance for an input signal at the amplifier. Some of the disclosed methods adjust impedance using switchable inductors to compensate for changes in impedance with changing gain modes. Some of the disclosed methods adjust a device size to compensate for changes in impedance with changing gain modes. By providing impedance adjustments, the amplifiers reduce losses and improve performance by improving impedance matching over a range of gain modes.

A receiver front end (300) having low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch (235) is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. A drain switch (260) is provided between the drain terminals of input FETs to place the input FETs in parallel. This increases the g.sub.m of the input stage of the amplifier, thus improving the noise figure of the amplifier.