In an example method of trimming a voltage reference circuit, the method includes: setting the circuit to a first temperature; trimming a first resistor (R.sub.DEGEN) of a differential amplifier stage of the circuit; and trimming a first resistor (R1) of a scaling amplifier stage of the circuit. The trimming equalizes current flow through the differential amplifier stage and the scaling amplifier stage. The method includes: trimming a second resistor (R2) of the scaling amplifier stage to set an output voltage of the circuit to a target voltage at the first temperature; setting the circuit to a second temperature; and trimming a second resistor (R.sub.PTAT) of the differential amplifier stage, a third resistor (R1.sub.PTAT) of the scaling amplifier stage, and a fourth resistor (R2.sub.PTAT) of the scaling amplifier stage to set the output voltage of the circuit to the target voltage at the second temperature.

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

The present disclosure provides for process and temperature compensation in a transimpedance amplifier (TIA) using a dual replica via monitoring an output of a first TIA (transimpedance amplifier) and a second TIA; configuring a first gain level of the first TIA based on a feedback resistance and a reference current applied at an input to the first TIA; configuring a second gain level of the second TIA and a third TIA based on a control voltage; and amplifying a received electrical current to generate an output voltage using the third TIA according to the second gain level. In some embodiments, one or both of the second TIA and the third TIA include a configurable feedback impedance used in compensating for changes in the second gain level due to a temperature of the respective second or third TIA via the configurable feedback impedance of the respective second or third TIA.

An enhanced current mirror can be utilized to accurately control a bias current associated with an amplifier. A current controller component (CCC) can employ the enhanced current mirror and can be associated with the amplifier. The CCC can comprise a comparator that can compare an adjusted supply voltage level to a reference voltage level, the adjusted supply voltage level relating to a supply voltage level of a supply voltage supplied to the amplifier and CCC. The CCC can control switching of an operational state of a transistor of the comparator to switch in or out a resistance of a reference resistor component associated with the supply voltage, based on a result of the comparison of the adjusted supply voltage level to the reference voltage level, to facilitate accurately controlling an amount of bias current associated with the amplifier. The CCC and amplifier can be situated on the same die.

A switching converter includes a voltage conversion circuit providing an output voltage from an input voltage and a PWM voltage generated in response to first and second oscillating voltages. The input stage of a transconductor circuit provides an input reference current following a difference between a reference voltage and a voltage dependent on the output voltage and according to a transconductance, and an output stage for providing an output reference current from the input reference current. A phase shifter shifts an oscillating reference voltage according to the output reference current to obtain the first and second oscillating voltages. The transconductance is controlled in response to the input voltage resulting in a change of the input reference current. Compensation for that change is provided by subtracting a variable compensation current from the input reference current, where the variable compensation current is generated in response to the input voltage.

An amplifier circuit includes a first input stage with a differential input transistor pair and a second gain stage having an output node coupled to a load. A node in the first gain stage is coupled to the output node in the second gain stage. A feedback line couples the output node to the control node of a first transistor of the differential input transistor pair. Current mirror circuitry is coupled to a current flow path through a further transistor in the second gain stage and includes a sensing node configured to produce a sensing signal indicative of the current supplied to the load. The sensing signal at the sensing node is directly fed back to the control node of the first transistor of the differential input transistor pair to provide a zero in the loop transfer function that is matched to and tracks and cancels out a load-dependent pole.

A bias structure includes a reference voltage node connected to gate structures of a first NMOS transistor and a second NMOS transistor, a bias voltage node comprising a bias voltage, and a first op amp having a first input connected to the reference voltage, a second input connected to a drain of the first NMOS transistor, and an output connected to gate structures of a first PMOS transistor and a second PMOS transistor. The bias structure further includes a second op amp having a first input connected to the reference voltage, a second input connected to a drain of the second NMOS transistor, and an output connected to a gate structure of a third NMOS transistor and the bias voltage node. The first NMOS transistor matches a transistor of a differential pair of an integrated circuit device.

A temperature compensation circuit is configured to generate a first electrical signal corresponding to the current ambient temperature, use the first electrical signal to adjust a second electrical signal received by an electrical signal input end, and obtain a third electrical signal; and output the third electrical signal to a power control circuit. The power control circuit is configured to convert the third electrical signal into a fourth electrical signal and output the fourth electrical signal to a power amplifier. The fourth electrical signal is used for controlling the gain of the power amplifier to present a preset change rule following a temperature change. Thus, by adding the described temperature compensation circuit in a power amplification circuit, the stability of the gain and the stability of the output power of a power amplifier are ensured, and the performance of the power amplifier is not affected by a change in temperature.

A high frequency circuit includes a transistor amplifying a high frequency signal, and having an input electrode and an output electrode, a line that is connected to any one of the input electrode and the output electrode, and transmits a high frequency signal or an amplified high frequency signal, a bias terminal to which a bias voltage is supplied, a bias circuit that has a first end connected to a first node and a second end connected to the bias terminal, and suppresses a high frequency signal having a frequency within an operating frequency band of the transistor from passing from the first node to the bias terminal, and a resonance circuit that is connected between a reference potential and a second node provided between the bias terminal and the bias circuit, and minimizes an impedance between the second node and the reference potential at a resonance frequency.

A MOSFET has a current conduction path between source and drain terminals. A gate terminal of the MOSFET receives an input signal to facilitate current conduction in the current conduction path as a result of a gate-to-source voltage reaching a threshold voltage. A body terminal of the MOSFET is coupled to body voltage control circuitry that is sensitive to the voltage at the gate terminal of the MOSFET. The body voltage control circuitry responds to a reduction in the voltage at the gate terminal of the MOSFET by increasing the body voltage of the MOSFET at the body terminal of the MOSFET. As a result, there is reduction in the threshold voltage. The circuit configuration is applicable to amplifier circuits, comparator circuits and current mirror circuits.