An amplification circuit includes a first switching circuit that includes input terminals and first and second output terminals and that puts the second output terminal into an open state with respect to the input terminals while selectively putting the first output terminal into a state of being connected to any of the input terminals or selectively puts the second output terminal into a state of being connected to any of input terminals while putting the first output terminal into a state of being open with respect to the input terminals; a matching network that is connected to the first output terminal; an amplifier that is connected to an output side of the matching network; a second switching circuit that is connected to an output side of the amplifier; and a bypass path that electrically connects the second output terminal and an output terminal of the second switching circuit. The amplifier is a variable-gain amplifier.

Embodiments of signal bias generators and regulators are described generally herein. Other embodiments may be described and claimed.

A device includes: a transistor having an input terminal configured to receive an input signal and to amplify the input signal; a bias current source configured to set a bias current of the input terminal of the transistor, the bias current source having a control input for receiving a control signal for selecting the bias current to have one of a plurality of selectable bias current levels; a bias resistance connected between the bias current source and the input terminal of the transistor; a bypass switch for selectively bypassing a first part of the bias resistance; and a control circuit for controlling the bypass switch to bypass the part of the bias resistance for a predefined time period in response to a change in the bias current level, and for controlling the bypass switch to stop bypassing the first part of the bias resistance after the predefined time period expires.

An inductor-less low noise amplifier (LNA) with high linearity is disclosed. The low noise amplifier includes: an input signal stage receiving an input signal; a first amplifier configured to receive the input signal, generate a first amplification signal by amplifying the received input signal, and output the generated first amplification signal, as a first output signal, to a first output terminal; a second amplifier configured to receive the input signal, generate a second amplification signal by amplifying the received input signal, and output the generated second amplification signal, as a second output signal, to a second output terminal; an output signal stage outputting a superimposition signal obtained by superimposing the first output signal and the second output signal; a first resistor feeding back the superimposition signal to the input signal stage; and a switch connecting/disconnecting between the input signal stage and the output signal stage.

A circuit configured to amplify a signal from which an offset is cancelled includes an amplifier including an input stage configured to receive an input signal, the amplifier configured to amplify the input signal and output the amplified signal, and a switch including a transistor configured to reset the amplifier in response to a reset signal, the transistor including a body node connecting the transistor to the circuit, the transistor being configured to form a current path between the body node of the transistor and the input stage of the amplifier.

A transceiver or RF front end employing a transformer with a low loss transmit/receive (T/R) switch circuit in the ground path. In various embodiments, differential outputs of a power amplifier are coupled to the first winding of the transformer, while the input of a low noise amplifier is coupled to the second side of the transformer via a matching inductor. The T/R switch circuit, which may be a thin oxide CMOS transistor, is coupled between the second side of the transformer and ground. In operation, the T/R switch circuit may be enabled during transmit mode operations of the power amplifier, such that a low impedance path to ground is provided at the input of the low noise amplifier, thereby protecting it from high voltage swings generated by the power amplifier.

A switching amplifier includes a plurality of cascade elements, each bridge circuit includes an inductive load coupled between a first leg terminal of one of the at least two leg circuits and a second leg terminal of another one of the at least two leg circuits. A first leg voltage of the first leg terminal have a phase shift relative to a second leg voltage of the second leg terminal, the phase shift is used for causing the inductive load to store electric energy and generating a minimum circulating current—I min or I min sufficient to effect conducting of a corresponding diode; each of the switches is configured to be turned on if the corresponding diode conducts current to effect zero voltage switching of the corresponding switch. The minimum circulating current—I min or I min is equal to a constant value.

The present disclosure relates to a device comprising two error amplifier stages having their first inputs interconnected, their second inputs interconnected and their outputs coupled to an output of the device, each stage comprising an operational amplifier; a circuit for calibrating the amplifier; a switch coupling an input of the amplifier to the first input; a switch coupling another input of the amplifier to the second input; a switch coupling an output of the amplifier to the stage output; a switch having on state which short-circuits the inputs of the amplifier; and a switch coupling the output of the amplifier to the calibration circuit.

A buffer circuit is provided. The buffer circuit includes a Current Differencing Transconductance Amplifier (CDTA) comprising a first input node and a second input node each configured to receive a respective one of a first signal and a second signal. The buffer circuit further includes a first source follower circuit coupled to a first output node of the CDTA and configured to generate a first buffer output signal based on a first output signal of the CDTA. Additionally, the buffer circuit includes a second source follower circuit coupled to a second output node of the CDTA and configured to generate a second buffer output signal based on a second output signal of the CDTA. The buffer circuit further includes a first feedback path comprising at least one of a first resistive element and a first capacitive element. The first feedback path couples an output node of the first source follower circuit to the first input node of the CDTA. In addition, the buffer circuit includes a second feedback path comprising at least one of a second resistive element and a second capacitive element. The second feedback path couples an output node of the second source follower circuit to the second input node of the CDTA.

A method for matching a pair of composite circuit elements (CEs) included in a circuit includes fabricating N CEs (e.g., resistors, transistors, current sources, capacitors) designed to match and switches configurable, according to M different combinations, to connect N/2 of the N CEs to form a first composite CE and to connect a remaining N/2 of the N CEs to form a second composite CE. Sequentially in time, for each combination of the M combinations, the switches are configured to form the first and second composite CEs according to the combination and a characteristic of the circuit is measured that includes the formed first and second composite CEs. The characteristic indicates how well the formed composite CEs match. A final combination of the M combinations is chosen whose measured characteristic indicates a best match and the final combination is used to configure the switches to form the composite CEs.