A power amplifier arrangement comprises a power amplifier comprising at least one transistor having a first gate and a second gate. The first gate is configured to receive a radio frequency input signal superimposed with a first control signal, and the second gate is configured to receive a second control signal. The first control signal is a linearization signal varying in relation to an envelope of the input signal and the second control signal is a temperature compensation signal varying in relation to a temperature of the power amplifier, or vice versa.

An amplifier system having: an amplifier having a linear operating region where an output signal produced by the amplifier at the output terminal has a power level increasing proportionally with the increasing input signal power level up to a compression region of the amplifier where the output power is inhibited from increasing with increasing input signal power; and a DC current limiting circuit, coupled between a DC power supply and the amplifier, to: supply DC current from the DC power supply that is equal to quiescent current to the amplifier from the DC power supply when the amplifier operates in the linear region; enable the amplifier to draw increasing DC current from the DC power supply above the quiescent current with increasing input signal power until the output signal power reaches the desired compression point level which is lower than that of a stand-alone amplifier without the DC current limiting circuit; and, then limits the current drawn by the amplifier from the DC power supply.

An exemplary FET includes a substrate and multiple vertically stacked layer groups with each layer group having a quantum well semiconductive layer and a nonconductive layer adjacent the first quantum well semiconductive layer. Conductive source and drain electrodes in conductive contact with the semiconductive layers. A 3-dimensional ridge of the stacked layer groups is defined between spaced apart first and second trenches which are between the source and drain electrodes. A continuous conductive side gate is disposed on the sides and top of the ridge for inducing a field into the semiconductive layers. A gate electrode is disposed in conductive contact with the conductive side gate.

The invention relates to a sequential broadband Doherty power amplifier with adjustable output power back-off The sequential broadband Doherty power amplifier has at least one input (I.sub.1, I.sub.2; RF.sub.in) for receiving at least one broadband HF signal, wherein the broadband HF signal or broadband HF signals (RF.sub.in) have at least an average power level (carrier/average) and a peak envelope power level (peak), with the average power level and the peak envelope power level defining a crest factor, and a first amplifier branch for amplifying the input signal, with the first amplifier branch providing the amplification substantially for the low and at least the average power level, at least one second amplifier branch for amplifying the input signal, wherein the second amplifier branch substantially provides the amplification for the peak envelope power level, wherein the output of the first amplifier branch is connected via an impedance inverter (Z.sub.T) to the output of the second amplifier branch, the junction (CN) being connected to the load (Z.sub.0) in a substantially directly impedance-matched manner, wherein the first and the second amplifier branch each have a supply voltage, with at least one of the supply voltages being variable as a function of the crest factor of the signal to be amplified, and wherein the signal propagation delay through the at least two amplifier branches is substantially identical in the operating range.

A Class-D amplifier includes a plurality of power rails, a quantizer, and a driver stage. The quantizer and the driver stage have a combined gain. For each power rail of the plurality of power rails, the Class-D amplifier senses a voltage value for the power rail and determines a ramp amplitude based on the sensed voltage value. The Class-D amplifier concurrently switches from the driver stage using a first power rail to a second power rail of the plurality of power rails and switches from the quantizer using the ramp amplitude associated with the first power rail to using the ramp amplitude associated with the second power rail so that the combined gain is constant.

Distributed amplifiers with controllable linearization are provided herein. In certain embodiments, a distributed amplifier includes a differential input transmission line, a differential output transmission line, and a plurality of differential distributed amplifier stages connected between the differential input transmission line and the differential output transmission line at different points or nodes. The distributed amplifier further includes a differential non-linearity cancellation stage connected between the differential input transmission line and the differential output transmission line and providing signal inversion relative to the differential distributed amplifier stages. The differential non-linearity cancellation stage operates with a separately controllable bias from the differential distributed amplifier stages, thereby providing a mechanism to control the linearity of the distributed amplifier.

A circuit arrangement for generating a current for an inductive load is provided. The circuit includes a switched output state, a modulator, a current measuring device, a controller, a compensator, and a summer The switched output stage is configured to generate the current from a supply voltage. The modulator is configured to modulate the supply voltage of the output stage depending on a modulator input signal of the modulator. The current measuring device is configured to determine the actual value of the current. The controller is configured to generate a controller signal depending on a setpoint value of the current and the actual value of the current. The compensator is configured to generate from the setpoint value of the current at least one compensation control signal that compensates for nonlinearities of the output stage. The summer is configured to generate the modulator input signal additively from the controller signal and the at least one compensation control signal.

Current monitoring techniques are included in an electronic system that provides power to a load from a power output stage that supplies power to a load. Multiple current control devices form the power output stage in series with multiple sense resistors that provide corresponding sense voltages indicative of current provided through the multiple current control devices to the load in the same or different time intervals. A calibration control circuit controls injection of current through the multiple sense resistors individually and measures the corresponding sense voltages generated by the current to determine resistance values of the multiple sense resistors. A correction subsystem computes a first ratio of a first resistance to a second resistance and a second ratio of a third resistance to a fourth resistance of the multiple sense resistors, and controls compensation for a difference between the first ratio and the second ratio to remove the measurement error.

An ultrasound probe buffer is provided. The ultrasound probe buffer may include a high impedance amplifier having a common-source core stage with series-series local feedback. The high impedance amplifier may include a first MOSFET and a second MOSFET, wherein a source terminal of the first MOSFET is coupled to a source terminal of the second MOSFET.

The input stage (16) of a high-fidelity amplifier (10) with high linearity and a low distortion rate comprises:—an input (12) for the digital signal to be converted;—a voltage output (26) for the converted voltage;—a digital/analog converter (20), the input of which forms the input (12) for the digital signal to be converted, the digital/analog converter (20) having access to a signal terminal (24);—a voltage current conversion resistor (36) arranged between the voltage output (26) and a reference potential; and—a current/voltage converter (22) that has a voltage output and is arranged between the signal terminal (24) and the voltage outlet (26). The current/voltage converter (22) comprises a transistor (46). The source of the transistor (46) is only connected to the signal terminal (24) of the digital/analog converter (20).