An electronic device may include wireless circuitry with a processor, a transceiver, an antenna, and a front-end module coupled between the transceiver and the antenna. The front-end module may include one or more power amplifiers for amplifying a signal for transmission through the antenna. A power amplifier may include a phase distortion compensation circuit. The phase distortion compensation circuit may include one or more n-type metal-oxide-semiconductor capacitors configured to receive a bias voltage. The bias voltage may be set to provide the proper amount of phase distortion compensation.

Methods and devices for reducing gate node instability of a differential cascode amplifier are presented. Ground return loops, and therefore corresponding parasitic inductances, are eliminated by using voltage symmetry at nodes of two cascode amplification legs of the differential cascode amplifier. Series connected capacitors are coupled between gate nodes of pairs of cascode amplifiers of the two cascode amplification legs so to create a common node connecting the two capacitors. In order to reduce peak to peak voltage variation at the common node under large signal conditions, a shunting capacitor is connected to the common node.

An on-chip transformer circuit is disclosed. The on-chip transformer circuit comprises a primary winding circuit comprising at least one turn of a primary conductive winding arranged as a first N-sided polygon in a first dielectric layer of a substrate; and a secondary winding circuit comprising at least one turn of a secondary conductive winding arranged as a second N-sided polygon in a second, different, dielectric layer of the substrate. In some embodiments, the primary winding circuit and the secondary winding circuit are arranged to overlap one another at predetermined locations along the primary conductive winding and the secondary conductive winding, wherein the predetermined locations comprise a number of locations less than all locations along the primary conductive winding and the secondary conductive winding.

A high-linearity amplifier including a main operational amplifier, a feedback circuit, and a compensation circuit is shown. The feedback circuit couples an output signal of the main operational amplifier to an input port of the main operational amplifier. The compensation circuit couples a former-stage circuit of the amplifier to the input port of the main operational amplifier to compensate for the non-linearity of the feedback circuit. The compensation circuit and the feedback circuit form an inverse paralleling linearization architecture. In the inverse paralleling linearization architecture, a resistor in the feedback circuit corresponds to a resistor in the compensation circuit which is biased in an inversed way in comparison with the corresponding resistor in the feedback circuit.

A switching amplifier system with a power supply, a pulse modulator configured to modulate an input signal into a pulse width modulation signal, a switching stage configured to generate an amplified output signal, and an error feedback signal configured to correct errors in the amplified output signal, where the input signal is comprised of at least one of an analog signal and a digital signal. A method of signal amplification comprising generating, by a pulse width modulator, a pulse width modulation signal, combining, by a switching stage, the input signal and the pulse width modulation signal to form an amplified output signal, and generating, by the switching stage, an error feedback signal, where the error feedback signal is configured to correct errors in the amplified output signal, and where the input signal is comprised of at least one of an analog signal and a digital signal.

A voltage-to-current converter circuit comprises an amplifier, a resistor, first and second feedback circuits, and an output circuit. The amplifier is configured to receive a differential input voltage signal. The resistor is coupled between first and second nodes of the amplifier. The first feedback circuit is coupled to a third node of the amplifier, provides feedback to the first and second nodes when the value of the input voltage signal is in a first range, and is turned off otherwise. The second feedback circuit is coupled to a fourth node of the amplifier, provides feedback to the first and second nodes when the value of the input voltage signal is in a second range different from the first range, and is turned off otherwise. The output circuit produces a differential current output signal having a value according to the value of the input voltage signal.

Differential amplifier circuitry including: first and second main transistors of a given conductivity type; and first and second auxiliary transistors of an opposite conductivity type, where the first and second main transistors are connected along first and second main current paths passing between first and second main voltage reference nodes and first and second output nodes, respectively, with their source terminals connected to the first and second output nodes, respectively, and with their gate terminals controlled by component input signals of a differential input signal; and the first and second auxiliary transistors are connected along first and second auxiliary current paths passing between first and second auxiliary voltage reference nodes and the first and second output nodes, respectively, with their drain terminals connected to the first and second output nodes, respectively, and with their gate terminals controlled by the component input signals of the differential input signal.

Differential amplifier circuitry including: first and second main transistors of a given conductivity type: and first and second auxiliary transistors of an opposite conductivity type, where the first and second main transistors are connected along first and second main current paths passing between first and second main voltage reference nodes and first and second output nodes, respectively, with their source terminals connected to the first and second output nodes, respectively, and with their gate terminals controlled by component input signals of a differential input signal; and the first and second auxiliary transistors are connected along first and second auxiliary current paths passing between first and second auxiliary voltage reference nodes and the first and second output nodes, respectively, with their drain terminals connected to the first and second output nodes, respectively, and with their gate terminals controlled by the component input signals of the differential input signal.

A circuit includes first through fourth transistors and a device. The first transistor has a control input and first and second current terminals. The control input provides a first input to the circuit. The second transistor has a control input and first and second current terminals. The control input provides a second input to the circuit. The third transistor has a control input and first and second current terminals. The fourth transistor has a control input and first and second current terminals. The second current terminal of the fourth transistor is coupled to the second current terminal of the third transistor, and the control input of the fourth transistor is coupled to the first current terminals of the first and second transistors. The device is configured to provide a fixed voltage to the control input of the third transistor.

A circuit includes a main amplifier having a first input and a first output. A main bias circuit is coupled to the main amplifier, and the main bias circuit configured to operate the main amplifier in a first frequency band. A feedforward cancellation amplifier has a second input and a second output, in which the second input is coupled to the first input, and the second output is coupled to the first output. A filter is coupled between the first input and the second input. A feedforward bias circuit is coupled to the feedforward cancellation amplifier. The feedforward bias circuit is configured to operate the feedforward cancellation amplifier in a second frequency band within and narrower than the first frequency band.