Methods and devices for reducing gate node instability of a differential cascode amplifier are presented. Ground return loops, and therefore corresponding parasitic inductances, are eliminated by using voltage symmetry at nodes of two cascode amplification legs of the differential cascode amplifier. Series connected capacitors are coupled between gate nodes of pairs of cascode amplifiers of the two cascode amplification legs so to create a common node connecting the two capacitors. In order to reduce peak to peak voltage variation at the common node under large signal conditions, a shunting capacitor is connected to the common node.

The present application discloses a transconductance amplifier and a related chip. The transconductance amplifier is configured to generate an output current according to a positive input voltage and a negative input voltage, wherein the transconductance amplifier includes: an input stage, configured to receive the positive input voltage and the negative input voltage and generate a positive output current and a negative output current, wherein the input stage includes: a first transistor, wherein a gate thereof is coupled to the positive input voltage; a second transistor, wherein a gate thereof is coupled to the negative input voltage; a first resistor, serially connected between the first transistor and the second transistor; a third transistor, wherein a source of the third transistor is coupled between the first resistor and the first transistor, and a drain of the third transistor is configured to output the positive output current; and a fourth transistor.

In accordance with an embodiment, a method includes determining an amplitude of an input signal provided by a capacitive signal source, compressing the input signal in an analog domain to form a compressed analog signal based on the determined amplitude, converting the compressed analog signal to a compressed digital signal, and decompressing the digital signal in a digital domain to form a decompressed digital signal. In an embodiment, compressing the analog signal includes adjusting a first gain of an amplifier coupled to the capacitive signal source, and decompressing the digital signal comprises adjusting a second gain of a digital processing block.

A transimpedance amplifier (TIA) structure includes an input node with a variable inductance component serving to reduce variation in peak amplitude over different gain conditions. According to certain embodiments, an inductor at the TIA input has a first node in communication with a Field Effect Transistor (FET) drain, and a second node in communication with the FET source. A control voltage applied to the FET gate effectively controls the input inductance by adding a variable impedance across the inductor. Under low gain conditions, lowering of inductance afforded by the control voltage applied to the FET reduces voltage peaking. TIAs in accordance with embodiments may be particularly suited to operate over a wide dynamic range to amplify incoming electrical signals received from a photodiode.

Systems and methods are provided for dynamic calibration of pre-distortion modification in transmitters. The pre-distortion modification may be applied during processing of an input signal for transmission, and feedback data, relating to the transmitter and/or processing performed after application of the pre-distortion modification in the transmitter, may be obtained. Adjustments to the pre-distortion modification may be determined based on the feedback data, and the adjustments to the pre-distortion modification may be applied in loop-back manner, thus enabling adjustment of pre-distortion modification dynamically based on real-time and current data. The pre-distortion modification may comprise modifying one or more signal characteristics, such as phase, frequency, and/or amplitude. Determining and/or applying the adjustments to the pre-distortion modification may be done periodically, based on one or more particular events, or conditionally.

For broadband data communication, a data signal voltage at a signal input node can be converted to an output signal current at a signal output node. A first transistor device can contribute to the output signal current, with its transconductance or other gain reduced to accommodate larger signal swings, at which a second transistor can turn on and increase an effective resistance value of at least a portion of a gain degeneration resistor associated with the first transistor device. The second transistor can also contribute to the output signal current to help maintain or enhance an overall gain between the signal input node and the signal output node. Multiple secondary stages, push-pull arrangements, buffer amplifier configurations (which may or may not contribute to current in the gain degeneration resistor), input and output transformers, negative feedback to help reduce component variability, and frequency modification circuits or components are also described.

Provided is an input voltage endurance protection architecture applied to a high-voltage operational amplifier with high input amplitude and high linearity. The input voltage endurance protection architecture includes three parts: a main operational amplifier, an auxiliary operational amplifier and an input stage voltage endurance protection circuit. The main operational amplifier is a high-voltage general-purpose operational amplifier, the auxiliary operational amplifier is a single-stage differential amplifier, and the single-stage differential operational amplifier is connected to a degeneration resistor Rbias. In addition, the auxiliary operational amplifier has a same connection method as the main operational amplifier at a positive input terminal and a negative input terminal, and both the positive input terminal and the negative input terminal are protected by an input stage voltage endurance protection circuit and receive and process input signals simultaneously.

The disclosure relates to a driver amplifier circuit. The driver amplifier circuit includes a non-linear differential amplifier and a non-linear resistor connected across output terminals of the differential amplifier. The non-linear resistor has a resistance value that increases as the differential voltage amplitude across the non-linear resistor increases. A transmitter may include the driver amplifier.

This application relates to amplifier circuitry and, in particular, to class-D amplifier circuits. The application describes amplifier circuitry (400) for receiving an input signal (Sin) and generating first and second driving signals (SoutP, SoutN) for driving a bridge-tied-load. The amplifier circuitry includes first and second class-D output stages (403p, 403n) for generating the first and second driving signals based on the input signal. A controller (406) controllably varies a common-mode component of the first and second driving signals based on an indication of amplitude of the first and second driving signals. The controller varies the common-mode component, at lower signal amplitudes, so the common-mode level of the first and second driving signals is moved away from an operating region that leads to distortion.

A Radio Frequency (RF) circuit including a receive path, a transmit path, a switching circuit, and an output configured to receive RF signals from an antenna in a receive mode of operation, and to provide RF signals to the antenna in a transmit mode of operation. The receive path is configured to be coupled between a low-noise amplifier and the output. The switching circuit is located in the receive path and is configured, in the receive mode, to selectively couple the low-noise amplifier to the output and to pass the received RF signals from the output to the low-noise amplifier. The transmit path is configured to be coupled between a power amplifier and the output, to provide, in the transmit mode, signals from the power amplifier to the output, bypassing the switching circuit, and to have, in receive mode of operation, an off-state impedance of at least 200+j*13 Ohm.