Patent classifications
H03F1/3217
HIGH LINEARITY LOW NOISE AMPLIFIER
An amplifier circuit is disclosed. The amplifier circuit includes an input terminal configured to receive an input signal, an output terminal configured to transmit an output signal, and a first signal path including a first amplifying circuit, where the first amplifying circuit is configured to receive the input signal and to transmit a first amplified output to the output terminal, and where the first amplified output includes first amplifier circuit harmonic noise. The amplifier circuit also includes a second signal path including a second amplifying circuit, where the second amplifying circuit receives the input signal and transmits a second amplified output to the output terminal, and where the second amplified output includes second amplifier circuit harmonic noise. The output signal includes the first and second amplified outputs, and the first amplifying circuit harmonic noise is at least partially canceled by the second amplifying circuit harmonic noise in the output signal.
High efficiency ultra-wideband amplifier
An amplifier comprising a current-biased active device, a voltage-biased active device, the voltage-biased active device and the current-biased active device are connected in series, to form a cascade of active devices, and an input terminal and an output terminal, the cascade of active devices connected between the input terminal and the output terminal, having an output terminal for driving a load impedance with an output signal in response to an input signal applied to the input terminal.
OUTPHASING AMPLIFIER AND SIGNAL PROCESSOR FOR OUTPHASING AMPLIFIER
An outphasing amplifier includes a first amplifier, a second amplifier, a first coupler coupling a first signal and a third signal, a second coupler coupling a second signal and a fourth signal, a first impedance converter inputting the first signal coupled with the third signal, a second impedance converter inputting the second signal coupled with the fourth signal, a combiner combining the first and the second signals output from the first and the second impedance converters and outputting an output signal, and a signal processor outputting the first signal having a first phase to the first amplifier, outputting the second signal having a second phase to the second amplifier, outputting the third signal having at least one of a third phase and a first amplitude to the first coupler, and outputting the fourth signal having at least one of a fourth phase and a second amplitude to the second coupler.
Amplification device
An amplification device comprising: a push pull circuit which amplifies an input signal; a diamond buffer circuit to which the signal which is amplified by the push pull circuit is input; and a current mirror circuit which is connected to a power supply and the diamond buffer circuit and is connected to a retraction current terminal of the push pull circuit.
Amplifier circuit having controllable output stage
The present invention provides an amplifier circuit, wherein the amplifier circuit includes a DAC, an output stage and a detector. In the operations of the amplifier circuit, the DAC is arranged for performing a digital-to-analog converting operation upon a digital input signal to generate an analog signal, the output stage is arranged for receiving the analog signal to generate an output signal, and the detector is arranged for detecting a characteristic of the input signal, and referring to the characteristic of the input signal to generate at least one control signal to adjust the output stage at a zero-crossing point of the output signal.
Method for improving feedback circuit performance
The disclosed technology relates to a method for improving performance of a feedback circuit comprising an amplifier and a feedback network, wherein the feedback circuit has at least one tunable component. In one aspect, the method comprises measuring first amplitude values at an input of the amplifier and second amplitude values at an output of the amplifier, estimating a linear open-loop gain of the amplifier based on both the amplitude values, estimating a linear finite gain error based on the estimated gain and the second amplitude values, subtracting the linear finite gain error from the first amplitude values to derive a set of samples containing second error information, deriving an signal-to-noise-plus-distortion ratio estimate based on the variance of the set of samples and a variance of the second amplitude values, and adjusting the feedback circuit in accordance with the signal-to-noise-plus-distortion ratio estimate.
POWER AMPLIFIER
A power amplifier includes a first amplifier configured to amplify an input signal and output, from a first output, a first signal in which the input signal is amplified, a second amplifier configured to amplify the first signal and output, from a second output, a second signal in which the first signal is amplified, a third amplifier configured to amplify the second signal and output, from a third output, a third signal in which the second signal is amplified, a capacitor connected between the first output and a mixing node, a first resistor connected between the second output and the mixing node, a first inductor connected between the third output and the mixing node, a second inductor connected between the mixing node and a load, and a feedback circuit configured to negatively feed back a mixed signal of the mixing node to an input of the first amplifier.
AMPLIFICATION DEVICE
An amplification device comprising: a push pull circuit which amplifies an input signal; a diamond buffer circuit to which the signal which is amplified by the push pull circuit is input; and a current mirror circuit which is connected to a power supply and the diamond buffer circuit and is connected to a retraction current terminal of the push pull circuit.
FULLY INTEGRATED CMOS MULTIPLE MOSFET-STACKED DOUBLE PUSH-PULL RF POWER AMPLIFIER
An amplification circuit for RF power amplifiers is provided. The circuit includes two PMOS amplification modules and two NMOS amplification modules; each module includes a CSCG structure composed of a stack of K transistors. The first PMOS module and the first NMOS module are connected in series between a supply voltage and ground; gates of main amplification transistors of the first PMOS module and the first NMOS module are connected to a non-inverting input, and outputs of the first PMOS module and the first NMOS module are connected together to form an inverting output. The second PMOS module and the second NMOS module are similarly connected. Both the first and the second modules will be connected side-by-side as a pseudo differential structure to provide double push-pull function to the load. The present disclosure simultaneously achieves high power efficiency, and high linearity.
System and method for reducing output harmonics
In one form, a signal generator system such as a power amplifier system includes an amplification stage, a lowpass filter, and a controller. The amplification stage includes a first amplifier having an input for receiving an input signal, a control input for receiving a first control signal, and an output. The lowpass filter has a first input coupled to the output of the first amplifier, and an output. The controller has a first input coupled to the output of the lowpass filter, and a first output coupled to the control input of the first amplifier, wherein the controller varies the first control signal to reduce a difference between the output of the lowpass filter and a first target voltage level.