A unit amplification circuit includes a push-pull circuit having a transistor with a gate connected to an input terminal, a symmetrical circuit connected symmetrically to the push-pull circuit and configured to be turned off in a first operation mode and turned on in a second operation mode, and a path control circuit connected to a drain of the transistor and configured to connect the drain and an output terminal in the first operation mode and to disconnect the drain and the output terminal in the second operation mode.

Systems and methods related to linear and efficient broadband power amplifiers are disclosed. In some embodiments, a method for amplifying a radio-frequency signal includes providing a Doherty amplifier circuit having a carrier amplification path and a peaking amplification path. The method includes receiving an radio-frequency signal and splitting the radio-frequency signal into a first portion and a second portion, the first portion provided to the carrier amplification path, the second portion provided to the peaking amplification path. The method further includes combining, using a balance to unbalance circuit, outputs of the carrier amplification path and the peaking amplification path to yield an amplified radio-frequency signal.

In some aspects, a programmable amplifier may comprise an n-channel metal-oxide-semiconductor (NMOS) amplification path and a complementary metal-oxide-semiconductor (CMOS) amplification path. In some aspects, the NMOS amplification path may include a first NMOS transistor and a second NMOS transistor that are connected in parallel between an input and an output. In some aspects, the CMOS amplification path may include a p-channel metal-oxide-semiconductor (PMOS) transistor connected in parallel with the first NMOS transistor between the input and the output. In some aspects, the programmable amplifier may further comprise a plurality of switches that are programmable to switch the PMOS transistor off in a first mode, such as an NMOS mode or a high linearity mode, and to switch the second NMOS transistor off in a second mode, such as a CMOS mode or a low current mode. Numerous other aspects are described.

Disclosed is a power amplifier system having a main amplifier with an input coupled to a main radio frequency (RF) input and an output connected to a main RF output, wherein the main amplifier exhibits a nonlinear gain characteristic with compression. At least one compression compensating amplifier has a signal input coupled to the common RF input and a signal output coupled to the common RF output.

An input buffer for an analog-to-digital converter, ADC, is provided. The input buffer is configured for receiving an input signal (V.sub.in) and for outputting an output signal (V.sub.out), and comprises an nMOS transistor and pMOS transistor. The nMOS transistor and the pMOS transistor are arranged in a push-pull configuration such that the input signal is fed to gates of the nMOS transistor and the pMOS transistor and the output signal is taken from sources of the nMOS and the pMOS transistors. The input buffer comprises a first varactor connected between a gate of the nMOS transistor and a first biasing voltage potential (V.sub.21), and a second varactor connected between a gate of the pMOS transistor and a second biasing voltage potential (V.sub.22), which are configured to reduce a signal amplitude dependency of a capacitance of the input buffer.

A signal amplifying circuit includes an amplifier and a common mode feedback circuit. The amplifier generates first and second outputs. The common mode feedback circuit receives the first and second outputs, and controls an output common mode voltage of the first and second outputs to a first reference voltage. The common mode feedback circuit includes an output common mode voltage detection circuit, a pull-up circuit and a pull-down circuit. The output common mode voltage detection circuit generates first and second control signals according to the output common mode voltage. The pull-up circuit with a first conduction degree controlled by the first control signal controls the output common mode voltage to be positively correlated with the first conduction degree. The pull-down circuit with a second conduction degree controlled by the second control signal controls the output common mode voltage to be negatively correlated with the second conduction degree.